200814252 九、發明說明： 【發明所展之技術領域】 本發明係有關於一種鑲嵌式影像感測晶片之封襞結 構’尤指一種鑲嵌式影像感測晶片，其中該承載座内緣係 呈p自梯狀’可以覆晶技術方式將影像感測晶片喪入一四 階内，且與該承載座周圍上之複數個金屬導腳相接合，令 其能做電性導通，並予以封裝包覆，有效提高產品製程效 率與薄型化者。 【先前技術】200814252 IX. Description of the Invention: [Technical Field] The present invention relates to a package structure for a mosaic image sensing wafer, and more particularly to a mosaic image sensing wafer, wherein the inner edge of the carrier is p The image-sensing wafer can be immersed into the first and fourth steps from the ladder-like flip-chip technology, and is bonded to a plurality of metal guide pins around the carrier to enable electrical conduction and encapsulation Effectively improve product process efficiency and thinner. [Prior Art]
隨著科技時代的日新月異，各式各樣的隨身資訊電子 產品以及設備因應而生，而各式的產品零組件均朝著輕薄 短小的目標邁進。如何使產品更具人性化，多機一體的概 念，體積縮小攜帶方便符合人因工程，更合乎消費者便利 追求時尚的需求，是目前市場主要的課題之—。而將手機 結合數位械魏甚至是MP3絲麵電腦，或是將 腦結合數位相機功能，即是其卜項重要之改良突破， 如何使其組裝更方便迅速，製造過程更簡單、體 薄，將是業界發展的主要目標。 言月參閱圖-所示，其係為習用影像感測晶片封裝辦 示意圖。習用之影像感測晶片封褒結構！係包括有··一^ ㈣二影像感測晶片u、_環堤12、複數金屬線/ =璃盍板14、以及若干錫球15。其_，職影像感須 S曰片設置於基板1〇上，以該複數金屬線U將該· 200814252 感測晶片11與該基板做電性導通。利用該環堤12環 繞該影像感測晶片11且設於該基板10上，用以保護該影 像感測晶片11以及與該基板10相導通之複數金屬線13, 進而於該環堤12上設置該玻璃蓋板14，使該影像感測晶 片11可透過該環堤12上所設之該玻璃蓋板14擷取外界 影像，並由該基板10下方所設之若干錫球15與其他電子 產品相連結者。 Φ 然而，習用之影像感測晶片封裝結構1，其影像感測 晶片11需以利用打金屬線13的方式，使該影像感測晶片 11與該基板10相互電性導通，且不易將影像感測晶片U 精密定位於固定之位置上，不僅組裝繁複更無法進一步達 到薄型化的需求。 【發明内容】 本發明之第一目的，在於提供一鑲嵌式影像感測晶月 • 之封裝結構，其係使用一中空且呈一階梯狀之承載座，可 將一影像感測晶片置於其中空處所預設之一凹階上，並與 該承载座上之一金屬導腳所延伸之一飛腳端相電性導 通，達到降低該封裝結構的高度之目的。 本發明之另一目的，在於提供一鑲嵌式影像感測晶月 之封裝結構，其係藉由該承載座内所預設之一凹階可將該 影像感測晶片以覆晶技術透過鑲卡方式定位於該預定凹 階内’無須使用高精度定位設備，可降低生產成本。 本發明之又一目的，在於提供一鑲嵌式影像感測晶月 7 200814252 之封裝結構，係利用一絕緣膠或一防靜電膠帶將該影像感 測晶片封裝於該承載座之凹階内，可使該影像感測晶片之 封裝結構不受其他電磁或靜電干擾者。。 為達上述之目的，本發明係提供一鑲嵌式影像感測晶 片之封裝結構，其係包括有：一承載座、一影像感測晶片、 一絕緣材料、以及一透明蓋板所組成。該承載座係具有預 定厚度之一中空框架，且周圍大致環繞有複數個金屬導 • 腳，並具有一第一表面以及一第二表面係以灌模或射出的 方式，將該複數個金屬導腳壓合並環繞於該承載座之中空 框架上。並且，該金屬導腳由該承載座之第二表面並延著 該中空框架厚度彎折並崁附於該第一表面上，進而往該承 載座中央中空處懸空延伸出一飛腳端。於該中空框架内緣 係呈一階梯狀環繞該承載座内緣，該階梯至少包括有一第 一凹階以及一第二凹階。 該影像感測晶片則包括有一作動面以及一非作動 馨面。該作動面可以覆晶技術鑲嵌於該承載座之第一凹階 處’使該影像感測晶Μ之作動面上—影像制區裸露於該 承載座之第-表面中央處。並利用以一 ^電材料將該影像 ' 制11顔之減餘墊触複數個金屬導腳之飛腳端 做電性導通。進而利用該絕緣材料將影像感測晶片之非作 動面於鱗二凹階處内包贿襄，使該影像制晶片之封 裝結構不受其他電磁或靜電干摄。 該透明蓋板健胁該轉座之該第一表面上，且藉 由-接著劑固定於該_座上。該承載座之第二表面上^ 8 200814252 金屬導腳可利用銲錫與一基板做電性導通，進而達到節省 製造成本以及更能使其達到輕薄短小的目的。 【實施方式】 為了能更清楚地描述本發明所提出之多鑲嵌式影像 感測晶片之封裝結構，以下將配合圖示詳細說明之。 請參閱圖二所示，圖二為本發明鑲嵌式影像感測晶片 之封裝結構第一較佳實施例立體分解視圖。其中，鑲嵌式 影像感測晶片之封裝結構2係包括：一承載座2〇、一影 像感測晶片30、一絕緣材料4〇 (另顯示於圖四）、以及一 透明蓋板50所共同組成。該承載座2〇包括有：一中空框 架2卜以及複數個金屬導腳22。該中空框架21更包括有： 一第一表面211、一第二表面212、一第一凹階213、以 及一第二凹階214。該影像感測晶片3〇包括有：一作動 面301、一非作動面302、一影像感測區31、以及複數個 鋁墊32。該金屬導腳22更包括有：一接合處221 (另顯 示於圖五A)以及一飛腳端222。 喷參閱圖二並配合圖二所示，其中，圖三為本發明 鑲肷式景>像感測晶片之封裝結構第一較佳實施例另一視 角之立體組合圖。如圖三所示，該承載座2〇可以是藉由 在一導線架（LeadFrame)上以灌模或射出的方式令該中 空框架21與導線架之該金屬導腳22相結合，且該中空框 架21係具有預定之厚度。於該中空框架21中央内緣處係 呈-階梯狀環繞，並由該承載座2〇之第二表& 212往該 9 200814252 第一表面211方向呈階梯狀漸縮，依序設置有該第二凹階 214以及第一凹階213。並且，該中空框架21之第二凹階 214所框圍之開口面積必須大於該第一凹階213所框圍之 開口面積，又該第一凹階213所框圍之開口面積與該影像 感測晶片30之該作動面301大致可相對應。 該影像感測晶片30係用來擷取外界影像，通常是電 荷輕合裝置（charge coupled device，CCD )或互補式金屬 • 氧化半導體（comPlementary metal oxide semieonduetoi·， CMOS)影像感測裝置。 該複數個金屬導腳22係為一平面條狀且大致呈放射 型態環繞於該接合處221 (另顯示於圖五a)，並嵌附於 該承载座20之中空框架213外緣表面上。並且，各別之 該金屬導腳22則由該承載座2〇之第一表面211嵌附並延 著該中空㈣21外緣之厚度彎折且細於該第二表面 212之上。再將其該接合處221 (另顯示於圖五A)予以 • 沖賴斷，使其該承載座20之第-絲211上之該金屬 導腳22留有-段懸空於該中空框架21中央透空處之該飛 腳编222。$亥金屬導腳22可以是銅、銘、合金、或其他 ‘ 導電金屬材料其中之一。 、 於該第一凹階213與該第—表面2H形成-適當之落 差南度’使該影像感測晶片30以覆晶技術駭於該第一 凹階222的同時’不僅使該影像感測晶片30之作動面301 夕圍可鑲卡於該第-_13上，更可將該影像感測晶片 之魏她塾3丨無金屬導腳Μ所延伸出之飛腳 200814252 端222恰可相對應。其兩者中央則留有一固定‘間隙，也 就是該第-凹階213與該第一表面211之落差高度，可利 用以一導電材料60塗佈於該間隙中，使該㉟塾3!與該金 屬導腳22之飛腳端222可做電性導通，藉以降低橋接時 短路之風險。在關時，可將該銘塾31所環繞之該影像 感測區32裸露於該承載座20之第一表面21丨中央，也就 是該中空框架21位於該第一表面211之中空處。該導電 材料60可以是冑轉鱗賊麵接紐術SMT、或以 錫球焊接其中之一。 请參間圖四並配合圖三所示，其中，圖四為本發明鑲 嵌式影像制晶狀封裝結娜—健實棚Α·Α剖視 圖。如圖四所示，該承載座2〇之第一凹階Μ]之垂直深 度hi與該第二凹階214之垂直深度h2必須大於或等於該 影像感測晶片30之厚度H。運用該承載座2〇之中空框架 21内所形成階梯狀之連續凹階處，以覆晶技術可輕易的 將該影像感測晶3〇片之作動面301嵌合於該承載座2〇 之第-凹階213 β，同時利用該導電材料6〇將該影像感 測晶片30上之銘墊32與該金屬導腳22之飛腳端222相 接合。並於該影像感測晶片30之該非作動面302上方， 也就是該中空框架21之第二凹階處214填入該絕緣材料 40且予以封裝，大體上可提供一屏障的效果，而能進一 步提供防電磁干擾（ΕΜΙ)的功效，並同時可保護該影像 感測晶片30於該承載座20内不受震動的影響。將該承載 座20之第一表面211上塗佈一接著劑70，可使其該透明 200814252 蓋板50 ϋ定於該承餘2G之上，藉轉賴影像感測晶 片30之影像感測區31不至被灰塵微粒所污染。該透明蓋 板50可以是紅外線渡光玻璃、素玻璃、抗反射玻璃及藍 玻璃其中之一。 哨參閱圖五A〜圖五Η所示，其中，圖五a〜圖五H 係為本發明賴式影像感測晶片之封裝結構製程示意 圖。如圖五A所示，該中空框架21之第一表面211結合 於該複數個金屬導腳22上，並令該金屬導腳22之接合處 221位於該中空框架21之中央透空處，且利用灌模或射 出成形的方式將該中空框架21之第二表面2 一 面211方向漸縮成階梯狀，並依序設置有該第二凹階214 與該第一凹階213。 如圖五B所示，將該各別之金屬導腳22延著該中空 緣之厚度彎折且炭附於該中空_21 n ^ = 五^所示，將該各別之金屬導腳r位於該中空 王”中央透空之接合處221以沖壓的方式予以截斷， =^!^空框架21之第—表面211上的該金屬 腳端222 /又懸空於該中央框架21中央透空處之該飛 腳端222，形成一完整的承載座20。 ㈣D所示，於該金屬導腳22之飛腳端扣表面 且朝向該承載座20之第二表面212處 電材料60。 獨等 如圖五E所示，將該影像感測晶片30之作動面3〇1 200814252 丨曰：Ιτ框架21之第一凹階213内，同時將該影像 6二二 上的_32利用該導電材料 60接合於該飛腳端上222之上，使該影晶片㈣該金屬 導腳22做電性導通；同時，使該影像感測晶片30之作動 面301上的該影像感測區31裸露於該中空框架21之 透空處。 、With the rapid development of the technology era, a variety of portable information electronic products and equipment have emerged, and all kinds of product components are moving toward a light, short and short goal. How to make the product more humane, the concept of multi-machine integration, the size is reduced, the carrying capacity is convenient to meet the human factor engineering, and it is more convenient for consumers. The pursuit of fashion is the main subject of the current market. Combining the mobile phone with the digital device Wei or even the MP3 silk computer, or combining the brain with the digital camera function, is an important improvement breakthrough of the sub-item, how to make it easier and faster to assemble, the manufacturing process is simpler and thinner, It is the main goal of the development of the industry. Referring to the figure - shown in the figure, it is a schematic diagram of a conventional image sensing chip package. Conventional image sensing chip sealing structure! The system includes a (4) two image sensing chip u, a ring bank 12, a plurality of metal wires / = glass plate 14, and a plurality of solder balls 15. The image sensor is disposed on the substrate 1 , and the 200814252 sensing wafer 11 is electrically connected to the substrate by the plurality of metal wires U. The image sensing wafer 11 is surrounded by the annular bank 12 and disposed on the substrate 10 for protecting the image sensing wafer 11 and the plurality of metal wires 13 connected to the substrate 10, and further disposed on the ring bank 12 The glass cover 14 allows the image sensing chip 11 to capture external images through the glass cover 14 disposed on the ring 12, and a plurality of solder balls 15 and other electronic products disposed under the substrate 10 Connected. Φ However, the image sensing chip 1 of the conventional image sensing chip 11 needs to electrically connect the image sensing wafer 11 and the substrate 10 by means of the metal wire 13, and it is difficult to sense the image. The wafer U is precisely positioned at a fixed position, which is not only complicated to assemble, but also cannot be further reduced in thickness. SUMMARY OF THE INVENTION A first object of the present invention is to provide a package structure for a mosaic image sensing lens, which uses a hollow and stepped carrier to place an image sensing wafer therein. The empty space is preset on one of the concave steps, and is electrically connected to one of the foot ends of one of the metal guide legs of the carrier to reduce the height of the package structure. Another object of the present invention is to provide a package structure for a mosaic image sensing crystal, which is capable of inserting the image sensing wafer by flip chip technology by using a recessed step preset in the carrier. The method is positioned within the predetermined concave step' without the need to use high-precision positioning equipment, which can reduce production costs. Another object of the present invention is to provide a package structure of the mosaic image sensing crystal moon 7 200814252, which is encapsulated in the concave step of the carrier by an insulating glue or an antistatic tape. The package structure of the image sensing chip is made free from other electromagnetic or static interference. . To achieve the above object, the present invention provides a package structure for a mosaic image sensing wafer, comprising: a carrier, an image sensing wafer, an insulating material, and a transparent cover. The carrier has a hollow frame of a predetermined thickness, and is surrounded by a plurality of metal guides and has a first surface and a second surface for filling or ejecting the plurality of metal guides. The foot press merges around the hollow frame of the carrier. Moreover, the metal guide leg is bent from the second surface of the carrier and extends along the thickness of the hollow frame and attached to the first surface, and then a flying foot end is suspended from the hollow portion of the central portion of the carrier. The inner edge of the hollow frame surrounds the inner edge of the carrier in a stepped manner, and the step includes at least a first concave step and a second concave step. The image sensing wafer includes an active surface and a non-active surface. The actuating surface may be flip-chip mounted on the first concave step of the carrier to make the image sensing area of the image sensing wafer exposed to the center of the first surface of the carrier. And using the electric material to make the image of the 11-thin reduction pad touches the foot ends of the plurality of metal guide pins for electrical conduction. Further, the insulating material is used to cover the non-actuating surface of the image sensing chip in the concave level of the scale, so that the sealing structure of the image forming wafer is not subjected to other electromagnetic or static dry shooting. The transparent cover is flanked by the first surface of the rotator and is secured to the pedestal by an adhesive. On the second surface of the carrier, the metal guide pin can be electrically connected to a substrate by using solder, thereby saving manufacturing cost and making it lighter and shorter. [Embodiment] In order to more clearly describe the package structure of the multi-mosaic image sensing chip proposed by the present invention, the following will be described in detail with reference to the drawings. Referring to FIG. 2, FIG. 2 is a perspective exploded view of a first preferred embodiment of a package structure of a mosaic image sensing wafer of the present invention. The package structure 2 of the mosaic image sensing chip comprises: a carrier 2 , an image sensing chip 30 , an insulating material 4 (also shown in FIG. 4 ), and a transparent cover 50 . The carrier 2 includes a hollow frame 2 and a plurality of metal guide legs 22. The hollow frame 21 further includes: a first surface 211, a second surface 212, a first concave step 213, and a second concave step 214. The image sensing wafer 3 includes an active surface 301, a non-actuating surface 302, an image sensing area 31, and a plurality of aluminum pads 32. The metal lead 22 further includes a joint 221 (shown in Figure 5A) and a foot end 222. Referring to FIG. 2 and FIG. 2, FIG. 3 is a perspective assembled view of another perspective view of the first preferred embodiment of the package structure of the inlaid-type scene of the present invention. As shown in FIG. 3, the carrier 2 can be combined with the metal lead 22 of the lead frame by filling or ejecting on a lead frame, and the hollow The frame 21 has a predetermined thickness. The central frame of the hollow frame 21 is surrounded by a step-like shape, and the second table & 212 of the carrier 2 is stepped toward the first surface 211 of the 9200814252, and is sequentially disposed. The second concave step 214 and the first concave step 213. The opening area of the second concave step 214 of the hollow frame 21 must be larger than the opening area of the first concave step 213, and the opening area of the first concave step 213 and the image sense. The actuating surface 301 of the test wafer 30 is substantially compliant. The image sensing chip 30 is used to capture an external image, typically a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) image sensing device. The plurality of metal guide legs 22 are in a planar strip shape and substantially radially radiate around the joint 221 (also shown in FIG. 5a) and are embedded on the outer surface of the hollow frame 213 of the carrier 20 . Moreover, the respective metal guide legs 22 are embedded by the first surface 211 of the carrier 2 and are bent and thinner than the second surface 212 by the thickness of the outer edge of the hollow (41) 21. Then, the joint 221 (shown in FIG. 5A) is further broken, so that the metal guide 22 on the first wire 211 of the carrier 20 is left with a segment suspended in the center of the hollow frame 21. The flying foot is 222. The $Metal metal lead 22 can be one of copper, metal, alloy, or other ‘conductive metal materials. Forming, in the first concave step 213 and the first surface 2H, a suitable drop south degree, so that the image sensing wafer 30 is flipped on the first concave step 222 while not only making the image sensing The actuating surface 301 of the wafer 30 can be mounted on the first -13, and the end of the flying probe 1214252 which extends from the metal-free guide pedal of the image sensing chip can be correspondingly matched. . The center of the two has a fixed 'gap, that is, the height difference between the first-concave step 213 and the first surface 211, and can be coated in the gap with a conductive material 60 to make the 35塾3! The foot end 222 of the metal lead 22 can be electrically connected to reduce the risk of short circuit during bridging. When closed, the image sensing area 32 surrounded by the cover 31 may be exposed in the center of the first surface 21 of the carrier 20, that is, the hollow frame 21 is located at the hollow of the first surface 211. The conductive material 60 may be a squash thief face joint SMT or one of solder balls. Please refer to Figure 4 and Figure 3 together. Figure 4 is a cross-sectional view of the inlaid image-forming crystal package of the invention. As shown in FIG. 4, the vertical depth hi of the first concave step 与 of the carrier 2 and the vertical depth h2 of the second concave step 214 must be greater than or equal to the thickness H of the image sensing wafer 30. By using the stepped continuous concave step formed in the hollow frame 21 of the bearing frame 2, the actuating surface 301 of the image sensing crystal 3 can be easily fitted into the bearing seat 2 by flip chip technology. The first recessed step 213 β is simultaneously bonded to the foot pad 222 of the metal lead 22 by the conductive material 6 . And encapsulating the insulating material 40 over the non-actuating surface 302 of the image sensing wafer 30, that is, the second recess 214 of the hollow frame 21, substantially providing a barrier effect, and further The anti-electromagnetic interference (ΕΜΙ) is provided, and at the same time, the image sensing wafer 30 is protected from vibration in the carrier 20. The first surface 211 of the carrier 20 is coated with an adhesive 70, so that the transparent 200814252 cover 50 is positioned on the residual 2G, and the image sensing area of the image sensing chip 30 is transferred. 31 is not contaminated by dust particles. The transparent cover 50 may be one of infrared ray glass, plain glass, anti-reflective glass, and blue glass. The whistle is shown in Figure 5A to Figure 5, wherein Figure 5a to Figure 5H are schematic diagrams of the package structure of the Lai image sensing chip of the present invention. As shown in FIG. 5A, the first surface 211 of the hollow frame 21 is coupled to the plurality of metal guiding legs 22, and the joint 221 of the metal guiding leg 22 is located at the central hollow of the hollow frame 21, and The second surface 2 of the hollow frame 21 is gradually tapered in a stepwise manner by filling or injection molding, and the second concave step 214 and the first concave step 213 are sequentially disposed. As shown in FIG. 5B, the respective metal guide legs 22 are bent along the thickness of the hollow edge and the carbon is attached to the hollow _21 n ^ = five^, and the respective metal guide pins r The joint 221 at the central hollow of the hollow king is cut by punching, and the metal foot end 222 on the first surface 211 of the empty frame 21 is again suspended in the central hollow of the central frame 21 The foot end 222 forms a complete carrier 20. As shown by D, the material of the foot of the metal foot 22 is buckled toward the second surface 212 of the carrier 20. As shown in FIG. 5E, the active surface of the image sensing wafer 30 is 〇1 200814252 丨曰: the first concave step 213 of the 框架τ frame 21, and the _32 of the image 6 2 is utilized by the conductive material 60. Bonding on the flying pin end 222 to electrically electrically connect the metal chip 22 of the shadow chip; and simultaneously exposing the image sensing area 31 on the active surface 301 of the image sensing chip 30 to the The hollow space of the hollow frame 21 is.
如圖JLF所示’於該影像感測晶片％之該非作動面 302後方，也就是該中空框架21之第二凹階處214填入 該絕緣材料40且予以封裝。 如圖五G所示，將該承載座20之第-表面211上塗 佈該接著#丨7〇，使其騎板Μ可峡於該承載座2〇 之第一表面211上。 如圖五H所示，將該承載座2〇位於第二表面212上 所嵌合之該金屬導腳22段，以選擇_設各狀該金屬 導腳22的方式，予以塗佈該導電材料，使其可與一電 路板100相接合並可做電性導通。 請參閱圖六所示，圖六為本發明鑲嵌式影像感測晶片 之封裝結構之組裝公差裕度示意圖。如@六所示，該金屬 導腳20之飛腳端222之寬度設計尺寸為15〇//m，且各別 之該飛腳端222間距為250#m。而一般該影像感測晶片 30上所設計之複數個鋁墊32尺寸為丨⑻私m見方，且該 各別銘塾32之間距為3〇〇# m。 該中空框架21係若以射出方式成形，其精度可以控 制最大誤差於±30//m之内，並於該中空框架21之第一凹 13 200814252 階213垂直側邊與置入之該影像感測晶片30之任意相對 侧邊各預留50/zm之容許裕度。故，該影像感測晶片3〇 鑲嵌入該第一凹階213時，可使該金屬導腳22之飛腳端 222與該影像感測晶片30之銘墊32接合時所產生之誤差 最大可達到±80//m的偏移。 但是，即使產生偏移誤差最大，該飛腳端222 仍有45//m寬度之區域重疊於相對應之該鋁墊32上。此 時，該紹墊32距離除了該所對應之飛腳端222外，另一 最接近之飛腳端222距離尚有195//m。由於該第一凹階 213與該飛腳端222中央則留有一固定之間隙，也就是該 第一凹階213與該第一表面211之落差高度，可將該導電 材料60運用此落差高度所形成之間隙塗佈於該飛腳端 222之上並與該鋁墊32相銲合做電性導通。例如以銲錫 作為該導電材料60時，當進行迴銲動作時可因熔融之金 屬表面張力，可將該銘墊32位置修正偏移且調整至所對 應之該飛腳端222正確位置處。 請參閱圖七所示，圖七為本發明鎮嵌式影像感測晶片 之封裝結狀帛二較佳實糊舰_。餘圖七之本發明 鑲嵌式影像制晶>{之封裝結構第二較佳實施例其大體 與圖四所*之第-較佳實狀賴式影像朗晶片之封 裝結構_ ’故相同之元件與結構以下將不再贊述。 如圖七所示，本發日月之第二較佳實施例不同點在於， 該中空框架21之第-凹階213與該第二凹階214之交接 處可設置為—導角215，使該影像感測晶片3G得以麵 200814252 藉由該導角215鎮提入該第一凹階213内。 請參閱圖八所示，圖八為本發明鑲嵌式影像感測晶片 之封裝結構之第三較佳實施例剖視圖。由於圖八之本發明 鑲嵌式影像感測晶片之封裝結構第三較佳實施例其大體 與圖四所示之第一較佳實施之鑲嵌式影像感測晶片之封 裝結構類似，故相同之元件與結構以下將不再贅述。 如圖八所示，本發明之第三較佳實施例不同點在於， 該承載座20’可以是以一載板以沖壓的方式形成連續階梯 狀内緣之該中空框架21’，且該中空框架21，夹層中設有 複數個導通孔216可貫穿於該中空框架21，之第一表面 211’以及第二表面212’。該載板之材質可以是玻璃布基有 環氧樹脂(FR-4、FR-5)、聚醯亞胺樹脂(pi)、Βτ樹脂、以 及聚苯醚樹脂(PPO)其中之一。 該金屬導腳22,可以是藉由將一金屬薄片（例如銅箔） 覆蓋於該載板之第一表面211，以及第二表面212,之上。 再運用沖壓或蝕刻的方式將該金屬薄片形成複數個金屬 導腳22’，並大致環繞於該第一表面211，與第二表面212, 之上，且利用該載板夾層中之該導通孔215將該第一表面 211’及第二表面212,之金屬導腳22,做電性導通。同時， 該第一表面211，之金屬導腳22,往該承載座20,中央中空 處係延伸出較具強度之飛腳端222,。 综上所述，本發明鑲嵌式影像感測晶片之封農結構， 其中’運用覆晶技術將該影像感測晶片30之作動面3〇1 録戾於該承載座20内所設置之該第一凹階213上，使該 15 200814252 影像感測晶片30上之鋁墊32與該金屬導腳22所延伸至 中央懸空處之該飛腳端222做電性導通，並於該承载座 20之第二凹階214内，且在該影像感測晶片30之非作動 面302上填入一絕緣材料4〇並予以封裝，使其具有防止 靜電或電磁干擾以及保護晶片之功效，更達到降低封裝結 構高度之目的。 以上所述係利用較佳實施例詳細說明本發明，而非限 制本發明之範圍。大凡熟知此類技藝人士皆能明瞭，適當 而作些微的改變及調整，仍將不失本發明之要義所在，亦 不脫離本發明之精神和範圍。 【圖式簡單說明】 圖一係為習用影像感測晶片封裝結構示意圖。 圖二係為本發明鑲嵌式影像感測晶片之封裝結構第 一較佳實施例立體分解視圖。 圖三係為本發明鑲嵌式影像感測晶片之封裝結構第 —較佳實施例另一視角之立體組合圖。 圖四係為本發明鑲嵌式影像感測晶片之封裝結構第 一較佳實施例A-A剖視圖。 圖五A〜圖五Η係為本發明鑲嵌式影像感測晶片之 封裝結構製程示意圖。 圖六係為本發明鑲嵌式影像感測晶片之封裝結構之 紐裝公差裕度示意圖。 圖七係為本發明镶欲式影像感剛晶片之封裝結構之 200814252 第二較佳實施例剖視圖。 圖八係為本發明鑲嵌式影像感測晶片之封裝結構之 第三較佳實施例剖視圖。 【主要元件符號說明】The insulating material 40 is filled in the rear of the non-actuating surface 302 of the image sensing wafer, as shown in Fig. JLF, and is encapsulated. As shown in Fig. 5G, the first surface 211 of the carrier 20 is coated with the next 〇7〇 so that it can ride on the first surface 211 of the carrier 2〇. As shown in FIG. 5H, the carrier 2 is located on the second surface 212 of the metal lead 22, and the conductive material is coated by selecting the metal lead 22. It can be joined to a circuit board 100 and can be electrically connected. Referring to FIG. 6, FIG. 6 is a schematic diagram showing the assembly tolerance margin of the package structure of the mosaic image sensing wafer of the present invention. As indicated by @六, the width of the foot end 222 of the metal guide pin 20 is 15 〇 / / m, and the distance between the respective foot end 222 is 250 # m. Generally, the plurality of aluminum pads 32 designed on the image sensing wafer 30 have a size of 丨 (8), and the distance between the individual dies 32 is 3 〇〇 # m. The hollow frame 21 is formed by injection, and the precision can be controlled within a maximum error of ±30//m, and the image is sensed on the vertical side of the first concave 13 200814252 step 213 of the hollow frame 21 A tolerance of 50/zm is reserved for any of the opposite sides of the wafer 30. Therefore, when the image sensing chip 3 is embedded in the first concave step 213, the error caused when the foot end 222 of the metal guiding pin 22 is engaged with the inscription pad 32 of the image sensing chip 30 is maximized. An offset of ±80//m is achieved. However, even if the offset error is maximized, the foot end 222 has an area of 45/m width overlapping the corresponding aluminum pad 32. At this time, the distance of the trailing pad 32 is 195//m from the other closest foot end 222 except for the corresponding foot end 222. Since the first concave step 213 and the center of the flying leg end 222 leave a fixed gap, that is, the height difference between the first concave step 213 and the first surface 211, the conductive material 60 can be applied to the height of the drop. A gap formed is applied over the flying leg end 222 and soldered to the aluminum pad 32 for electrical conduction. For example, when solder is used as the conductive material 60, the position of the pad 32 can be corrected and shifted to the correct position of the corresponding foot end 222 due to the molten metal surface tension during the reflow operation. Referring to FIG. 7, FIG. 7 is a packaged junction of the in-well image sensing chip of the present invention. The second preferred embodiment of the package structure of the present invention is substantially the same as the package structure of the first-best-like real image-mounting chip of FIG. The components and structures will not be described below. As shown in FIG. 7, the second preferred embodiment of the present invention differs in that the intersection of the first concave step 213 and the second concave step 214 of the hollow frame 21 can be set to a guide angle 215, so that The image sensing wafer 3G is lifted into the first recess 213 by the guide angle 215 by the surface 200814252. Referring to FIG. 8, FIG. 8 is a cross-sectional view showing a package structure of a mosaic image sensing wafer according to a third preferred embodiment of the present invention. The third preferred embodiment of the packaged image sensing chip package of the present invention is substantially similar to the package structure of the first preferred embodiment of the mosaic image sensing chip shown in FIG. And the structure will not be described below. As shown in FIG. 8 , the third preferred embodiment of the present invention is different in that the carrier 20 ′ can be a hollow frame 21 ′ which is formed by pressing a continuous stepped inner edge by a carrier plate, and the hollow In the frame 21, a plurality of through holes 216 are formed in the interlayer to penetrate the first surface 211' and the second surface 212' of the hollow frame 21. The material of the carrier may be one of a glass cloth based epoxy resin (FR-4, FR-5), a polyimide resin (pi), a yoke resin, and a polyphenylene ether resin (PPO). The metal lead 22 can be overlaid on the first surface 211 of the carrier and the second surface 212 by a metal foil (e.g., copper foil). Forming the metal foil into a plurality of metal lead legs 22' by stamping or etching, and substantially surrounding the first surface 211, and the second surface 212, and utilizing the via holes in the carrier interlayer 215 electrically conductive the first surface 211 ′ and the second surface 212 of the metal lead 22 . At the same time, the first surface 211, the metal guide leg 22 extends toward the carrier 20 and the central hollow portion extends the relatively strong foot end 222. In summary, the sealing structure of the mosaic image sensing chip of the present invention, wherein the image of the image sensing wafer 30 is recorded by the flip chip technology in the carrier 20 a recess 213, the aluminum pad 32 on the 15200814252 image sensing chip 30 and the metal foot 22 extending to the central floating point of the foot end 222 electrically conductive, and the carrier 20 The second concave step 214 is filled with an insulating material 4 on the non-actuating surface 302 of the image sensing wafer 30 and encapsulated to prevent static electricity or electromagnetic interference and protect the wafer, thereby reducing the package. The purpose of the height of the structure. The above description of the present invention is intended to be illustrative of the preferred embodiments of the invention. It will be apparent to those skilled in the art that such modifications and adaptations may be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram of a conventional image sensing chip package structure. 2 is a perspective exploded view of a first preferred embodiment of a package structure of a mosaic image sensing wafer of the present invention. 3 is a perspective assembled view of another perspective view of a package structure of the mosaic image sensing chip of the present invention. Figure 4 is a cross-sectional view showing the first preferred embodiment A-A of the package structure of the mosaic image sensing chip of the present invention. FIG. 5A to FIG. 5 are schematic diagrams showing the process of packaging structure of the mosaic image sensing chip of the present invention. Figure 6 is a schematic diagram showing the margin tolerance of the package of the mosaic image sensing chip of the present invention. Figure 7 is a cross-sectional view showing a second preferred embodiment of the package structure of the inlaid image sensing chip of the present invention. Figure 8 is a cross-sectional view showing a third preferred embodiment of the package structure of the mosaic image sensing chip of the present invention. [Main component symbol description]
1〜習用之影像感測晶片封裝結構 10〜基板 11〜影像感測晶片 12〜環堤 13〜金屬線 14〜玻璃蓋板 15〜锡球 2〜鑲嵌式影像感測晶片之封裝結構 20、20’〜承載座 21、21’〜中空框架 211、21Γ〜第一表面 212、212’〜第二表面 213、213’〜第一凹階 214、214,〜第二凹階 215〜導角 216〜導通孔 22、22’〜金屬導腳 221〜接合處 222、222’〜飛腳端 30〜影像感測晶片 301〜作動面 302〜非作動面 31〜影像感測區 32〜鋁墊 40〜絕緣材料 50〜透明蓋板 60〜導電材料 100〜電路板 70〜接著劑 171 ~ conventional image sensing chip package structure 10 ~ substrate 11 ~ image sensing wafer 12 ~ ring bank 13 ~ metal wire 14 ~ glass cover 15 ~ solder ball 2 ~ mosaic image sensing chip package structure 20, 20 '~bearing seat 21, 21'~ hollow frame 211, 21Γ~first surface 212, 212'~ second surface 213, 213'~ first concave step 214, 214, ~ second concave step 215 ~ lead angle 216~ Vias 22, 22' to metal pins 221 to 222, 222' to foot end 30 to image sensing wafer 301 to active surface 302 to non-active surface 31 to image sensing area 32 to aluminum pad 40 to insulation Material 50 ~ transparent cover 60 ~ conductive material 100 ~ circuit board 70 ~ adhesive 17