JP2005093551A - Package structure and packaging method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the manufacturing cost, reduce the size and weight, generalize various device mountings, facilitate customization, facilitate testing before packaging, reduce the manufacturing cost, and increase the functionality of the structure. The package structure and packaging method thereof are provided.
Semiconductor substrates 20b and 20a are mounted on upper and lower surfaces of an interposer 10a made of a flexible and electrically insulating base material, and molded with a molding resin 24 to form a COF, and an upper surface of a package substrate 40 The semiconductor chip 20c is mounted on the semiconductor chip 20c, and a plurality of COFs are stacked on the package substrate 40 to constitute a SIP (system in package).
[Selection] Figure 7

Description

  The present invention relates to a package structure of a chip-like semiconductor device and a packaging method thereof.

  In an electronic device using a semiconductor device such as a terminal device (mobile phone) of a mobile communication system, the point is how to increase the integration of the semiconductor device in order to reduce the size and weight. As described above, when the miniaturization of the semiconductor circuit is proceeding smoothly, the circuit as much as possible is made into one chip, and the advantages of reducing the mounting area, increasing the speed, and reducing the power consumption have been utilized. However, problems such as a rapid increase in manufacturing cost and a prolonged design and development period due to miniaturization of semiconductor circuits have become apparent.

  Therefore, SIP (system in package) technology that three-dimensionally mounts a plurality of semiconductor chips has attracted attention. For example, Non-Patent Document 1 discloses a CSP (chip size package) using a flexible carrier as shown in FIG. A double-sided chip mounting type three-dimensional mounting package as shown in FIG.

  FIG. 15 is a cross-sectional view showing the package structure of the semiconductor device of Non-Patent Document 1. The semiconductor chips 20a and 20b are mounted on flexible interposers 10a and 10b, end surfaces of the interposers 10a and 10b are bent to the back surfaces of the semiconductor chips 20a and 20b, and the layers are stacked and connected with solder bumps.

In the example shown in FIG. 16, the semiconductor chip 20 is mounted on both surfaces of the central portion of the interposers 10a, 10b, 10c, and 10d, and bumps 30 projecting downward are formed on the peripheral portions of the interposers 10a to 10d. The layers of the interposer are connected via bumps.
NEC Laboratories “Development of 3D packaging technology for LSI chips that achieve the world's smallest size”, [Search September 9, 2003], Internet <URL: http://www.labs.nec.co.jp/ Topics / data / r021127 / ＞ North "NMTI-Product Overview" [searched September 9, 2003], Internet <URL: http://www.northcorp.co.jp/Current/indexJ.htm>

  Such conventional SIPs have a problem that the structure is complicated and the manufacturing cost increases. Further, the structure shown in FIG. 15 has a problem that it cannot be applied to a system having a large number of input / output signal lines because the number of bumps that can be formed is limited. In the structure shown in FIG. 16, there is a problem that the thickness dimension is increased over the whole, and a relatively large space is required at a portion connecting the interposers forming the layers. Further, in the conventional SIP, since all the semiconductor chips are basically mounted and packaged, the operation characteristics cannot be tested and the quality can be judged. This is a problem in improving the yield rate. For example, if even one of the stacked semiconductor chips is defective, the entire SIP becomes a defective product, and the overall non-defective product rate is reduced, leading to an increase in cost.

  In addition, in conventional SIP, multiple types of semiconductor chips having different functions can be combined. However, since development is performed on the premise of a predetermined combination of chips at the time of SIP development, the assembled SIP naturally has the expected functions. I couldn't get much of the equipment I had.

  Furthermore, in the conventional SIP, a plurality of semiconductor chips are stacked and arranged to reduce the size of the whole, but the structure of the stacked arrangement is not always utilized. For example, the thermal resistance around the semiconductor chip increases due to the downsizing of the SIP, but in order to enhance the heat dissipation effect, only a design is adopted in which a material having high thermal conductivity is used for the mold resin.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a package structure of a semiconductor device and a packaging method thereof, which are reduced in manufacturing cost and reduced in size and weight.

  Another object of the present invention is to provide a package structure of a semiconductor device that can be easily customized by enhancing versatility for various element mountings, and a packaging method thereof.

  It is another object of the present invention to provide a package structure of a semiconductor device and a packaging method thereof, which can easily test the semiconductor device and reduce the manufacturing cost before packaging.

  Another object of the present invention is to provide a package structure of a semiconductor device and a packaging method thereof that not only achieves downsizing by arranging a plurality of semiconductor elements in a stacked manner but also enhances structural functionality.

  The present invention provides an interposer (substrate) in which an internal terminal to which a terminal of a semiconductor element is connected, an external terminal for external connection, and a conductor wiring that electrically connects the external terminal and the internal terminal are formed. In the package structure of a semiconductor device provided with a plurality of semiconductor element mounting interposers in which semiconductor elements are mounted on the interposer, the interposer has a base made of a flexible electrical insulator, and a bowl shape is substantially rectangular. By arranging external terminals on the peripheral edge, stacking the semiconductor element mounting interposers, and joining the external terminals together without providing a terminal member on the surface of the external terminals to separate the adjacent interposers. The semiconductor element mounting interposer is integrated.

  The present invention also provides an interposer in which an internal terminal to which a terminal of a semiconductor element is connected, an external terminal for external connection, and a conductor wiring that electrically connects the external terminal and the internal terminal are formed. In a semiconductor device package structure having a semiconductor element mounting interposer having a semiconductor element mounted thereon, an internal terminal to which an external terminal of the semiconductor element mounting interposer mounted on the upper surface is connected and an external terminal for connection to a mounting substrate A package substrate having a terminal and a conductor wiring that electrically connects the external terminal and the internal terminal, and the interposer has a base shape made of a flexible electrical insulator, Is formed in a substantially rectangular shape, and the external terminals are arranged on the periphery, and the semiconductor element mount-in is connected to the external terminals of the semiconductor element mount interposer. Without providing a terminal member for separating the Poza and the package substrate, it is characterized in that it has joined the external terminal to the internal terminal of the package substrate.

  Further, the present invention is characterized in that a plurality of the semiconductor element mount interposers are provided, and each interposer is stacked on the package substrate.

  The present invention also provides an interposer in which an internal terminal to which a terminal of a semiconductor element is connected, an external terminal for external connection, and a conductor wiring that electrically connects the external terminal and the internal terminal are formed. In the package structure of the semiconductor device provided with the semiconductor element mounting interposer in which the semiconductor element is mounted on the inner terminal for connecting to the external terminal of the semiconductor element mounting interposer mounted on the upper surface, and for connecting to the mounting substrate A package substrate having external terminals and conductive wirings for electrically connecting the external terminals and the internal terminals is provided, and the interposer has a bowl shape that is substantially rectangular and the external terminals are arranged on the peripheral edge. The external terminal of the semiconductor element mount interposer and the internal terminal of the package substrate are connected via a wire. There.

  The present invention also provides an interposer in which an internal terminal to which a terminal of a semiconductor element is connected, an external terminal for external connection, and a conductor wiring that electrically connects the external terminal and the internal terminal are formed. In a package structure of a semiconductor device having a plurality of semiconductor element mounting interposers each having a semiconductor element mounted thereon, a slot portion having an internal terminal into which a peripheral portion of the interposer is inserted and an external terminal of the interposer is electrically connected And a package substrate on which an external terminal for connection to the mounting substrate and a conductor wiring for electrically connecting the external terminal and the internal terminal of the slot portion are formed, and the interposer has a flexible base material It is made of a conductive electrical insulator, and the bowl shape is substantially rectangular, and external terminals are arranged on the periphery, and the external terminals of each interposer are slotted. It is characterized in that were passed to the internal terminal parts.

  Further, according to the present invention, a functional layer having a thermal property or a mechanical property different from that of the base material of the interposer or the mold material around the base material is provided between the layers of the semiconductor element mount interposers arranged in a stacked manner. It is characterized by.

  In addition, according to the present invention, thermal characteristics or mechanical characteristics differ between the substrate of the interposer, the package substrate, or the mold material around the interposer and the package substrate between the semiconductor element mount interposer and the package substrate. It is characterized by providing a functional layer.

  Furthermore, the present invention is characterized in that the functional layer is provided between two or more layers, and the plurality of functional layers include a plurality of types of functional layers having different thermal characteristics or mechanical characteristics. .

  According to the present invention, the external terminals are arranged on the peripheral edge of the interposer, and the external terminals are provided as spacers for separating adjacent interposers or without providing a terminal member for increasing the overall rigidity of the interposer. By integrating a plurality of interposers by joining the external terminals of adjacent interposers, the structure of the interposer itself is simplified, the manufacture thereof is facilitated, and the cost can be reduced. Further, the laminated portion of the external terminals of the interposer becomes thin, and a thinner package structure can be obtained. In addition, since the semiconductor element mount interposer having an external terminal at the peripheral portion acts as a single package by itself, the test using the external terminal is facilitated, and the characteristic measurement and pass / fail judgment can be made at that stage. Therefore, it is possible to package only a non-defective semiconductor element mount interposer, and it is possible to greatly improve the non-defective rate without causing an increase in cost.

  In addition, according to the present invention, by mounting the semiconductor element mounting interposer on the package substrate, the above-described effects can be obtained, and the package can be mounted on the mounting substrate of the electronic device by a conventional method. A semiconductor device is obtained.

  In addition, according to the present invention, a plurality of semiconductor elements can be integrated without increasing the external dimensions of the package substrate by stacking and arranging a plurality of interposers each mounted with a semiconductor element on the package substrate.

  In addition, according to the present invention, by connecting the external terminal of the semiconductor element mount interposer and the internal terminal of the package substrate via the wire, the structure of the interposer itself is simplified, and its manufacture becomes easy. Cost can be reduced.

  In addition, according to the present invention, the semiconductor device mount includes a slot portion into which the peripheral portion of the interposer is inserted into the package substrate, and the peripheral portion of the interposer is inserted into the slot portion to integrate them. A combination of a plurality of units is obtained in the unit of the interposer. Therefore, it is possible to easily configure the semiconductor device using only the non-defective unit by performing the test in units of the semiconductor element mount interposer. Also, by standardizing the external terminals in units of the semiconductor element mount interposer, the versatility of the semiconductor element mount interposer can be improved. For example, since the semiconductor element mount interposer can be selected according to the characteristics and specifications of the device to be finally obtained, the degree of freedom in design becomes extremely high.

  In addition, according to the present invention, only a semiconductor element mount interposer is provided by interposing a functional layer having different thermal characteristics or mechanical characteristics from the base material of the interposer between the layers of the semiconductor element mount interposers arranged in a stacked manner. A semiconductor device having higher functionality in terms of thermal characteristics or mechanical characteristics can be obtained as compared with a structure in which the layers are laminated or a structure in which the periphery of the structure is molded.

  In addition, according to the present invention, a functional layer having a thermal characteristic or mechanical characteristic different from that of any of the interposer, the package substrate, and the surrounding molding material is interposed between the layers of the interposer and the package substrate. A semiconductor device having high functionality with respect to thermal characteristics or mechanical characteristics can be obtained.

  According to the invention, the functional layer is provided between two or more layers, and the plurality of functional layers include a plurality of types of functional layers having different thermal characteristics or mechanical characteristics. As a result, a semiconductor device having not only a small structure but also higher functionality can be obtained.

A package structure and packaging method of a semiconductor device according to the first embodiment will be described with reference to FIGS.
1A is a top view of a packaged semiconductor device, FIG. 1B is a front view thereof, FIG. 1C is a top view of a package substrate which is a component thereof, and FIG. 1D is an overall view of the packaged semiconductor device. It is a front view.

  As will be described later, the interposer 10 is a flexible substrate made of polyimide as a base material. The semiconductor chip 20b is mounted at the center of the upper surface and the semiconductor chip 20a is mounted at a position facing the lower surface. External terminals 13 of the interposer are arrayed at the peripheral edge of the interposer 10 (in this example, positions along the left and right sides in the figure). Further, semiconductor chips 20b and 20a are mounted on the upper and lower surfaces of the interposer 10 to form internal terminals for electrical connection with the terminals of the semiconductor chip. Conductor wirings (not shown) that electrically connect the internal terminals and the external terminals 13 are formed on the upper surface, the lower surface, or, if necessary, an internal layer of the interposer 10. In this way, it has a structure equivalent to COF (chip on film). A structure made up of this interposer and a semiconductor chip mounted thereon is hereinafter simply referred to as “COF”.

  The package substrate 40 is a hard substrate as compared to the interposer 10, and the internal terminals 42 are arrayed and formed on the periphery of the upper surface (in this example, positions along the left and right sides in the figure). On the upper surface of the package substrate 40, internal terminals that are electrically connected to the terminals of the semiconductor chip 20c are formed. Furthermore, external terminals (bumps) 43 are formed on the lower surface of the package substrate 40 for mounting on a mounting substrate of an electronic device to be incorporated. Between the external terminal 43 and the internal terminal 42, between the internal terminal where the terminal of the semiconductor chip 20c conducts and the external terminal 43, and further, the internal terminal where the terminal of the semiconductor chip 20c conducts and the peripheral internal terminal 42 Conductor wirings are formed between the two.

  The semiconductor device shown in FIG. 1 includes a step of mounting the semiconductor chips 20 a and 20 b on the interposer 10 to form a COF, a step of mounting the semiconductor chip 20 c on the package substrate 40, and the package substrate 40. On the other hand, it is packaged by a step of pressing the terminal portion of the interposer 10 of the COF. If necessary, thereafter, the entire upper portion of the package substrate 40 is molded with the mold resin 24 as shown in FIG.

  2A is a partial cross-sectional view showing the mounting structure of the semiconductor chip with respect to the interposer, FIG. 2B is a partial cross-sectional view showing the mounting structure of the semiconductor chip with respect to the package substrate, and FIG. 2C is a connection portion of the interposer with respect to the package substrate. It is a fragmentary sectional view which shows a structure. (D) is a fragmentary sectional view which shows another structure of the connection part of the interposer with respect to a package board | substrate.

  The base material 11 of the interposer 10 is made of polyimide, and as shown in FIG. Gold (Au) bumps 22 are provided on the terminals (pads) of the semiconductor chips 20 a and 20 b and bonded to the internal terminals 12 of the interposer 10. An underfill (resin adhesive) 23 is filled in the gap between the interposer 10 and the semiconductor chips 20a and 20b. For this bonding, a pressure welding method or an ultrasonic bonding method is used. In addition, a conductive paste bonding method in which a conductive adhesive is provided between the gold bump 22 and the internal terminal 12 or a solder bonding method using a high-temperature solder (Sn-Ag solder) bump instead of the gold bump may be employed. .

  The upper and lower conductor wirings including the internal terminal 12 of the interposer 10 are electrically connected via bumps (vias) 14 inside the interposer.

  The mounting structure of the semiconductor chip with respect to the package substrate 40 is the same as the mounting structure of the semiconductor chip with respect to the interposer 10, and the gold bumps 22 of the semiconductor chip 20c are attached to the internal terminals 42 on the upper surface of the package substrate 40 as shown in FIG. It is joined. An underfill 23 is filled between the semiconductor chip 20 c and the package substrate 40.

  On the upper surface of the base 41 of the package substrate 40, internal terminals 42 of the package substrate are formed as shown in FIG. An external terminal 13 is formed on the lower surface of the base material 11 of the interposer 10. The external terminals 13 of the interposer are electrically and mechanically joined by press-contacting with the internal terminals 42 of the package substrate. Since the conductors on the upper and lower surfaces of the interposer 10 are integrated in the thickness direction of the interposer 10 via the bumps 14 provided in the interposer base material 11, there is no significant deformation at the inner bump 14 portion during pressure contact. . Therefore, the external terminal 13 of the interposer can apply a bonding load at a predetermined location to the internal terminal 42 of the package substrate, and a highly reliable pressure contact can be performed.

  The COF may be mounted on the package substrate 40 through solder as shown in FIG. That is, the internal terminals 42 of the package substrate 40 and the external terminals 13 of the interposer 10 may be made conductive with solder. In this case, solder balls are formed in advance on the interposer 10 side or the package substrate side, the two are aligned, and a predetermined pressure and a predetermined temperature are applied for bonding.

  Copper (Cu) bumps 431 are formed on the lower surface of the base material 41 of the package substrate 40, and solder balls 432 are further formed around the copper (Cu) bumps 431. A BGA type package is configured by arranging the copper bumps 431 and the solder balls 432 in a grid array. When this semiconductor device is mounted on a mounting board of an electronic device, it is surface-mounted via the solder balls 432.

Specific examples of dimensions and structures of the respective parts of the semiconductor device shown in FIG. 1 are as follows.
<COF>
(1) Size Semiconductor chip to be mounted 10 mm × 10 mm × 50 μm to 100 μm
Interposer 12mm × 12mm × 40μm
(2) External terminals Number of terminals (30-40) x 2 sides (60-80 if placed on one side only)
Terminal pitch 400μm ~ 150μm
<Package substrate side>
(1) Size Semiconductor chip to be mounted 10 mm × 10 mm × 50 μm to 100 μm
Package substrate itself 12mm × 12mm × 200μm ~ 400μm
(2) BGA
Number of balls 300-400
<Overall size>
15mm x 15mm x (1.2-1.4mm)
(A margin of about 100 μm between the COF lower surface after mounting and the upper surface of the semiconductor chip on the package substrate side)
Thus, the height H of the semiconductor device can be reduced to about 1.2 to 1.4 mm. However, this is the maximum height of the central portion of the semiconductor device, and since the peripheral portion of the interposer 10 is bent toward the package substrate 40, the thickness dimension of the peripheral portion of the semiconductor device can be made thinner than the central portion. .

  When the upper part of the package substrate is resin-molded, the thickness of the mold resin in the COF external terminal forming part and the internal terminal forming part of the package substrate is determined from the laminated portion of the semiconductor chips 20a, 20b, 20c (the central part of the package substrate). It may be thinned. As a result, the size of the peripheral portion of the packaged semiconductor device can be reduced.

Next, a manufacturing process of an interposer in which an external terminal can be pressed against an internal terminal of the package substrate will be described.
FIG. 3 is a cross-sectional view at each stage of the process. First, as shown in (a), a copper plate having a thickness of about 50 μm is used as a starting material, a photosensitive resist film is applied and formed on both sides thereof as shown in (b), and after drying, a mask is formed as shown in (c). Then, it is developed and a resist film having a predetermined pattern is formed as shown in FIG. Further, unnecessary copper portions are removed by etching as shown in (e), and a truncated cone-shaped bump 14 is formed as shown in (f) by resist stripping. Thereafter, as shown in (g), polyimide is laminated, and a copper foil is stacked on the surface from which the bump protrudes and hot-pressed. Thereafter, as shown in (i), by patterning into a predetermined shape by photolithography, polyimide is used as a base material, and a predetermined conductor pattern is provided on both sides thereof, and upper and lower conductors are joined by internal bumps at predetermined locations. Get the structure interposer.

  FIG. 4 shows the package structure of the semiconductor device according to the second embodiment. 1 is different from the apparatus shown in FIG. 1 in the arrangement shape of terminals provided on the package substrate 40 and the interposer 10. That is, in the example shown in FIG. 4, the internal terminals 42 are arranged near the four sides of the peripheral portion of the package substrate 40, and the external terminals 13 are arranged and formed on the four sides of the peripheral portion of the interposer 10. Thus, by arranging the terminals on the package substrate 40 side and the interposer 10 side on four sides, a larger number of terminals can be provided.

  In the first and second embodiments, the terminals on the package substrate 40 side and the interposer 10 side are rectangular, but the terminal shape is not limited to this. For example, a square, a circle, an oval, an ellipse are used. It may be a shape. Further, the terminals do not have to be arranged in a line, and may be arranged in a staggered manner, for example. In the example shown in FIG. 4, the upper portion of the package substrate and the periphery of the semiconductor chip of the COF are left exposed. However, the upper portion of the package substrate and the periphery of the semiconductor chip of the COF may be resin-molded. At that time, the thickness of the mold resin in the external terminal forming part of the COF and the internal terminal forming part of the package substrate can be made thinner than the laminated part (the central part of the package substrate) of the semiconductor chips 20a, 20b, 20c, and the packaged semiconductor is accordingly produced. The size of the peripheral portion of the device can be reduced.

  FIG. 5 shows a package structure of a semiconductor device according to the seventh embodiment. (A) is a top view thereof, and (B) is a front view thereof. Unlike the apparatus shown in FIG. 1, in the example shown in FIG. 5, the periphery of the semiconductor chips 20 a and 20 b mounted on the interposer 10 is molded with a molding resin 24. By resin molding in this way, the semiconductor chips 20a and 20b can be protected, and the semiconductor chips 20a and 20b are not affected by the surrounding environment, so that the working environment standards are relaxed and the handling of the COF is facilitated.

  In FIG. 5, in order to clarify the boundary between the semiconductor chip mount interposer and the package substrate, the semiconductor chip 20 c and the mold resin 24 are drawn with a space, but the semiconductor chip 20 c on the package substrate 40 side is drawn. The mold resin 24 on the interposer side may be in contact with. As a result, it is possible to reduce the thickness while maintaining electrical insulation between the semiconductor chip on the package substrate side and the semiconductor chip on the interposer side.

  Since the interposer in the state where the semiconductor chip is mounted as described above has the external terminals 13 on the peripheral edge thereof, the peripheral edge of the interposer 10 is crimped and applied to a test apparatus that is electrically connected to the external terminals 13. Thus, an operation test of the COF can be performed. The package substrate on which the semiconductor chip is mounted also has external terminals formed on its lower surface, so it has internal terminals on the upper surface that are connected to the external terminals on the interposer side. Operation test can be performed by electrical connection. Therefore, by combining a package substrate on which a non-defective semiconductor chip is mounted and a COF on which a non-defective semiconductor chip is mounted, a combination of one of the defective products and the other non-defective product is eliminated, and the semiconductor device as a product The rate of non-defective products can be increased.

  FIG. 6 shows a package structure of a semiconductor device according to the fourth embodiment. (A) is a top view, (B) is the front view. Unlike the semiconductor device shown in FIG. 5, in the example shown in FIG. 6, terminals are formed on the four sides of the interposer 10 and the four sides of the package substrate 40 and connected to each other. Further, in the example shown in FIG. 6, the four corners of the interposer 10 are notched so that when connecting to the terminals of the package substrate 40, the terminal portions can be easily bent without applying excessive stress. I have to. Thereby, a highly reliable joining state can be obtained for all terminals.

  Also in the third and fourth embodiments, the upper part of the package substrate 40 and the periphery of the COF semiconductor chip may be resin-molded. At that time, if the thickness of the mold resin of the external terminal forming portion of the COF and the internal terminal forming portion of the package substrate is reduced, the size of the peripheral portion of the entire packaged semiconductor device can be reduced accordingly. Furthermore, the package substrate and the COF may be integrated by filling the resin only in the gap between the upper surface of the package substrate 40 and the COF.

  FIG. 7 shows a package structure of a semiconductor device according to the fifth embodiment. In this example, a plurality of COFs are stacked on the package substrate. A semiconductor chip 20 c is mounted on the upper surface of the package substrate 40, and the upper portion thereof is molded with a mold resin 24. Semiconductor chips 20b and 20a are mounted on the upper and lower surfaces of the interposer 10a, and the periphery thereof is molded with a mold resin 24. Similarly, semiconductor chips 20d and 20e are mounted on the upper and lower surfaces of the interposer 10b, and the periphery thereof is molded with a mold resin 24. FIG. 7B is a partial cross-sectional view showing the structure of the joint of two COFs with respect to the package substrate. In this example, external terminals 13a and 13a ′ are formed on the lower surface of the base material 11a of the interposer 10a, and upper surface terminals 15 and wiring conductors 16a that are electrically connected to each other through the internal bumps 14 are formed on the upper surface. Yes. Further, external terminals 13b are formed on the lower surface of the base material 11b of the upper interposer 10b, and wiring conductors 16a electrically connected to the external terminals 13b are formed on the upper surface via the internal bumps 14 on the upper surface. doing. Internal terminals 42, 42 ′ are formed on the upper surface of the base material 41 of the package substrate 40.

  When a plurality of COFs are stacked on the package substrate as described above, the lowermost COF interposer is first bonded to the package substrate. That is, the external terminals 13a and 13a 'of the interposer 10a are pressed into contact with the internal terminals 42 and 42' of the package substrate 40, respectively. Next, the external terminal 13b of the upper interposer is pressed into contact with the upper surface terminal 15 of the lower interposer. Alternatively, a plurality of COF interposers may be stacked on the package substrate 40 and mechanically pressed at the same time, and ultrasonic waves may be applied as necessary to press the terminals between the layers simultaneously.

  The terminals of each layer may be soldered (braded) with solder. At that time, the lowermost COF interposer is first brazed to the package substrate, and then the external terminal 13b of the upper interposer is brazed to the upper surface terminal 15 of the lower interposer. Alternatively, a plurality of COF interposers may be stacked on the package substrate 40 and simultaneously pressed and heated to solder the terminals between the layers simultaneously.

  With such a structure, the wiring conductor 16a of the lower interposer is electrically connected to the internal terminal 42 'on the package substrate side via the bump 14 and the external terminal 13a'. Further, the wiring conductor 16b of the upper interposer is electrically connected through a route of bump 14 → terminal 13b → terminal 15 → bump 14 → terminal 13a → terminal 42.

  In the example shown in FIG. 7B, in order to guide the wiring conductor 16b of the upper interposer to the terminal on the package substrate 40 side, the bumps 14 inside the interposer are arranged so as to be stacked on the same axis. Therefore, an appropriate pressing force can be applied to the surfaces of the terminals facing each other at the time of pressure contact, and the pressure contact can be reliably performed. However, the present invention is not limited to this, and may be routed to a predetermined location via the wiring conductor of the lower interposer in order to guide the wiring of the upper interposer to the package substrate. Further, the internal terminals 42 and 42 'of the package substrate and the external terminals 13a and 13a' of the interposer may be joined by soldering as shown in FIG. Similarly, the terminals between the lower interposer and the upper interposer may be soldered together via solder.

  In the above example, the package substrate 40 is joined in order from the lower interposer to the upper interposer. However, the interposers are joined together in a unit state, and the unit is mounted on the upper surface of the package substrate. You may make it do.

  Further, in the example shown in FIG. 7B, the example in which the external terminals formed in each interposer are independently connected to the internal terminals of the package substrate is shown. However, for example, the same signal line as a bus line is used. In the case of common connection, the predetermined signal lines of the COF may be connected together and connected to the internal terminals on the package substrate. Furthermore, predetermined signal lines of the interposer may be joined to each other independently of the signal lines on the package substrate.

  FIG. 8 is a view showing a package structure of a semiconductor device according to the sixth embodiment. Unlike the package structure shown in FIG. 7, in the example of FIG. 8, the terminals of both the interposers 10 a and 10 b are directly attached to the terminals on the upper surface of the package substrate 40. That is, on the upper surface of the package substrate 40, internal terminals for joining the external terminals of the respective interposers are formed. In the case of such a structure, the lower interposer 10a is attached to the upper surface of the package substrate 40, and then the upper interposer 10b is attached. For joining the terminals, copper (Cu) pressure welding or soldering is applied.

  In the structure shown in FIG. 8, since the structure of the external terminal forming portion of each interposer is simplified, the manufacture thereof is facilitated. In addition, since the terminal arrangement is independent for each interposer, even when the terminal pitch is different for each interposer, it can be easily handled. Further, when a test is performed for each COF unit, electrical connection between the terminal and the test apparatus can be easily performed.

  Also in the fifth and sixth embodiments, the upper part of the package substrate 40 and the periphery of the semiconductor chip of the COF may be resin-molded. At that time, if the thickness of the mold resin of the external terminal forming portion of the COF and the internal terminal forming portion of the package substrate is reduced, the size of the peripheral portion of the entire packaged semiconductor device can be reduced accordingly.

  FIG. 9 is a view showing a package structure of a semiconductor device and a packaging method thereof according to the seventh embodiment. In this example, the semiconductor device is packaged using a plurality of COFs without using a hard package substrate. In FIG. 9A, a mounting board 50 is a mounting board (circuit board) of an electronic device on which the packaged semiconductor device is to be mounted. In this example, the semiconductor chip 20 f is flip-chip bonded to the upper surface of the mounting substrate 50. The semiconductor device 100 is mounted on the mounting substrate 50 so as to cover the semiconductor chip 20f.

  FIG. 9B is a partial cross-sectional view showing the structure of the external terminal portion of the lower interposer 10a. External terminals 17 for mounting on a mounting board are formed on the lower surface of the base material 11 of the interposer 10a. In this example, in order to perform solder ball connection, a copper bump 171 is formed, and a solder ball 172 is formed around the copper bump 171. Upper surface terminals 15 for connecting external terminals of the upper interposer are formed on the upper surface of the base material 11 of the interposer 10a. The joining structure between the interposers is the same as that shown in FIG.

  The semiconductor device 100 may be resin-molded except for the terminal portion for connecting to the mounting substrate 50. Further, after the semiconductor device 100 is mounted on the mounting substrate 50, the periphery of the semiconductor device 100 may be resin-molded.

  FIG. 10 is a diagram showing a package structure of a semiconductor device and a packaging method thereof according to the eighth embodiment. In the example shown in FIG. 2, a copper foil is pressed against the lower surface of the interposer (the surface facing the package substrate) to make the entire surface substantially flat. For example, at the stage shown in step (g) of FIG. The tip of the internal bump (via) 14 protrudes from the lower surface of the substrate 11. An interposer in such a state may be used.

  In FIG. 10, the bumps inside the interposer are crushed as shown in FIG. 10B by pressing the interposer 10 toward the package substrate 40 with a predetermined pressure from the state shown in FIG. The lower surface of the interposer 10 is pressed against the upper surface of the package substrate 40. Therefore, the thickness dimension of the interposer 10 can be reduced while the bumps are provided, and the overall thickness of the packaged semiconductor device can be reduced.

  FIG. 11 is a view showing a package structure of a semiconductor device and a packaging method thereof according to the ninth embodiment. In each of the embodiments shown so far, the external terminal of the interposer is directly pressed or brazed to the internal terminal of the package substrate, but in this example, wire bonding is performed. In FIG. 11, the interposer 10 includes a semiconductor chip 20a on the lower surface and a semiconductor chip 20b on the upper surface, thereby forming a COF. External terminals are formed on the upper surface of the interposer 10. Bumps 43 are formed as external terminals on the lower surface of the package substrate 40, and internal terminals are formed on the upper surface. The COF is bonded to the upper surface of the package substrate 40, and the external terminals on the upper surface of the interposer 10 and the internal terminals on the upper surface of the package substrate 40 are connected by wires W. Thereafter, if necessary, the entire upper surface of the package substrate 40 is resin-molded to protect the entire wire bonding portion together with the COF.

  FIG. 12 is a view showing the main part of the package structure of the semiconductor device according to the tenth embodiment. In each of the embodiments described so far, the example in which the semiconductor chip is mounted on the interposer only by the flip chip bonding method is shown, but in this example, wire bonding is used together. In the example shown in FIG. 12A, the semiconductor chip 20a is flip-chip bonded to the lower surface of the interposer 10. The semiconductor chip 20b is die-bonded on the upper surface, and the semiconductor chip 20d is further bonded to the upper surface. The semiconductor chip 20b and the internal terminal on the upper surface of the interposer 10 are connected by a wire W2. Further, the semiconductor chips 20d and 20b are connected by a wire W1.

  In the example shown in (B), the semiconductor chip 20 a is flip-chip bonded to the lower surface of the interposer 10. The semiconductor chip 20b is Philip chip bonded to the upper surface, and the semiconductor chip 20d is die bonded to the upper surface. The semiconductor chip 20d and the internal terminal on the upper surface of the interposer 10 are connected by a wire W.

  In both examples (A) and (B), another semiconductor chip 20e is flip-chip bonded to the wire bonding side (upper surface) of the interposer 10, but this element is not a semiconductor chip such as a chip capacitor or the like. The chip element may be used.

  The COF shown in FIG. 12 is packaged by mounting it on one or more package substrates. When a plurality of COFs are mounted on the package substrate, the COF of the type shown in FIG. 12 may be combined with the COF already shown in another embodiment. In this way, by stacking other semiconductor chips directly on the semiconductor chip, many chips can be packaged inside without increasing the number of interposers and the overall thickness.

  FIG. 13 is two cross-sectional views showing the package structure of the semiconductor device and the packaging method thereof according to the eleventh embodiment. In the example shown in (A), a slot base 44 is provided on the upper portion of the package substrate 40. The slot base 44 is provided with slots 441, 442, and 443 for inserting peripheral portions (edge portions) in which external terminals of the interposers 10a, 10b, and 10c that are part of COFa, COFb, and COFc are arranged. Yes. The inner surfaces of these slots are provided with terminals that contact the external terminals of the interposers 10a, 10b, and 10c. The package substrate 40 is provided with a COF holding portion 45 for mechanically fixing the other end of the interposer of COFa, COFb, and COFc.

  The external terminals of COFa, COFb, and COFc and the terminals in the slot are standardized, and a plurality of types of COFs are selected and inserted into the slots of the slot base 44 to be packaged. For example, a COF having a data processing semiconductor chip, a COF having a memory chip, and a COF having a peripheral device interface chip can be combined to form a semiconductor device that performs one function. .

  In the example shown in FIG. 13B, slots 441, 442, and 443 are provided on the upper portion of the package substrate 40, respectively. Unlike the case of (A), in the structure of (B), each slot is arranged on the plane of the package substrate 40. Therefore, the slot portion can be made thin.

  Each COF may be detachable from the slot, or the function may not be changed thereafter by resin-molding the entire upper portion of the package substrate 40 after being inserted once.

This semiconductor device performs an overall operation test in a state where a predetermined COF is mounted, determines whether each COF is good or bad by a test program, and finally replaces a COF that is regarded as defective. The semiconductor device may be configured as follows,
If each COF unit is connected to a test device to make a pass / fail judgment, and only non-defective COFs are combined and inserted into each slot, the yield rate can be increased extremely efficiently.

FIG. 14 is a cross-sectional view showing the package structure of the semiconductor device according to the twelfth embodiment. (A) joins three COFs (COFa, COFb, COFc) electrically and mechanically at the end of their interposers. Here, 61, 62, 63, and 64 are sheet materials, respectively, and these sheet materials are different in thermal characteristics or mechanical characteristics from the base material of the COF interposer. For example, the sheet material 61 is a Peltier element, absorbs heat generated from the COFa semiconductor chip, and efficiently dissipates the heat to the mounting substrate side on which the semiconductor device 100 is mounted. Further, the sheet material 62 is made of a material having higher elasticity than the base material of the interposer, and performs electrical insulation and absorption of mechanical shock between the semiconductor chip on the upper surface of COFa and the semiconductor chip on the lower surface of COFb. The sheet material 63 is made of a material having higher heat insulating properties than the base material of the interposer, and acts as a heat insulating material for insulating heat from COFb and COFa. The sheet material 64 is made of a COFc interposer base material or a material having a higher thermal conductivity (lower thermal resistance) than the sheet material 63, and keeps the COFc semiconductor chip as close to the ambient temperature as possible.
The semiconductor device 100 may be resin-molded except for the terminal portion for connection to the mounting substrate.

  In the example shown in FIG. 14B, the semiconductor chip 20c is mounted on the upper surface of the package substrate 40, and two COFs (COFa, COFb) are stacked on the upper surface of the package substrate 40. The sheet material 61 is inserted between the semiconductor chip 20c and COFa, and the sheet material 62 is inserted between COFa and COFb. However, in this example, since the periphery of each semiconductor chip is resin-molded, the sheet materials 61 and 62 are sandwiched between the mold resins. These sheet materials 61 and 62 have different thermal characteristics or mechanical characteristics from the base material of the interposer of COFa and COFb and the mold resin, and impart new functions thermally or mechanically. For example, the semiconductor chip 20c is protected from impact by using a material having a higher shock absorption than the mold resin as the sheet material 61. Further, by using a material having a smaller thermal resistance than the mold resin as the sheet material 62, the heat generated from the COFa semiconductor chip is efficiently radiated upward.

  In the example shown in FIG. 14, the functional layer is composed of a sheet material previously formed into a sheet shape, but the functional layer is formed by applying a predetermined functional material to the surface of the semiconductor chip or by molding. May be configured. Furthermore, a functional material may be applied to the surface of the mold resin.

  In each of the embodiments described above, the semiconductor chip is mounted on the interposer by flip chip mounting, but may be resin-molded after wire bonding. Similarly, a semiconductor chip may be mounted on the package substrate side by wire bonding and resin molded.

  Further, although an example in which solder balls are arranged in a grid array on the mounting surface side of the package substrate is shown, a pin grid array (PGA) structure in which pins are arranged in a grid may be used.

  Moreover, although each embodiment showed the example which mounted only the semiconductor chip, you may mount passive elements, such as a chip capacitor and chip resistance, in one or both of an interposer and a package board | substrate.

  Furthermore, in each of the above-described embodiments, the example in which only the periphery of the semiconductor chip or the entire semiconductor device is molded has been described, but only the terminal portion that connects the interposers or the terminal portion that connects the package substrate and the interposer. Resin molding may be performed to ensure security and enhance the environmental resistance of the terminal portion.

The figure which shows the package structure of the semiconductor device which concerns on 1st Embodiment. The figure which shows the structure of each part of the semiconductor device, and the packaging method Diagram showing interposer manufacturing process The figure which shows the package structure of the semiconductor device which concerns on 2nd Embodiment. The figure which shows the package structure of the semiconductor device which concerns on 3rd Embodiment. The figure which shows the package structure of the semiconductor device which concerns on 4th Embodiment The figure which shows the package structure of the semiconductor device which concerns on 5th Embodiment The figure which shows the package structure of the semiconductor device which concerns on 6th Embodiment The figure which shows the package structure of the semiconductor device which concerns on 7th Embodiment The figure which shows the principal part of the package structure of the semiconductor device which concerns on 8th Embodiment. The figure which shows the package structure of the semiconductor device which concerns on 9th Embodiment The figure which shows the principal part of the package structure of the semiconductor device which concerns on 10th Embodiment The figure which shows the package structure of the semiconductor device which concerns on 11th Embodiment The figure which shows the package structure of the semiconductor device which concerns on 12th Embodiment The figure which shows the package structure of the conventional semiconductor device The figure which shows the package structure of another conventional semiconductor device

Explanation of symbols

10-Interposer 11-Base material of interposer 12-Internal terminal of interposer 13-External terminal of interposer 14-Internal bump (via) of interposer
15-Interposer upper surface terminal 16-Interposer wiring conductor 17-Interposer external terminal (bump)
171-copper bump 172-solder ball 20-semiconductor chip 22-semiconductor chip bump 23-underfill 24-mold resin 30-bump 31-stiffener 40-package substrate 41-base material of package substrate 42-internal terminal of package substrate 43-External terminal (bump) of package substrate
431-copper bump 432-solder ball 44-slot body 441, 442, 443-slot 45-COF holding part 50-mounting substrate 61-64-sheet material 100-semiconductor device

Claims (11)

The semiconductor element is mounted on an interposer formed with an internal terminal to which the terminal of the semiconductor element is connected, an external terminal for external connection, and a conductor wiring that electrically connects the external terminal and the internal terminal. In the package structure of a semiconductor device provided with a plurality of semiconductor element mount interposers,
The interposer has a base material made of a flexible electrical insulator, a bowl shape is substantially rectangular and the outer terminals are arranged on the peripheral edge, and the semiconductor element mount interposers are stacked and arranged. A package structure for a semiconductor device, wherein a plurality of semiconductor element mount interposers are integrated by joining external terminals without providing a terminal member for separating adjacent interposers on the surface of the external terminals. The semiconductor element is mounted on an interposer formed with an internal terminal to which the terminal of the semiconductor element is connected, an external terminal for external connection, and a conductor wiring that electrically connects the external terminal and the internal terminal. In the package structure of a semiconductor device having a semiconductor element mount interposer,
An internal terminal to which an external terminal of a semiconductor element mounting interposer mounted on the upper surface is connected; an external terminal for connection to a mounting substrate; and a conductor wiring for electrically connecting the external terminal and the internal terminal; A package substrate formed with
The interposer has a base material made of a flexible electrical insulator, a bowl shape is substantially rectangular, and the external terminals are arranged on a peripheral portion, and the external terminals of the semiconductor element mount interposer are A package structure of a semiconductor device, wherein an external terminal is joined to an internal terminal of the package substrate without providing a terminal member for separating the semiconductor element mount interposer and the package substrate.   The package structure of the semiconductor device according to claim 2, wherein a plurality of the semiconductor element mount interposers are provided, and each interposer is stacked on the package substrate. The semiconductor element is mounted on an interposer formed with an internal terminal to which the terminal of the semiconductor element is connected, an external terminal for external connection, and a conductor wiring that electrically connects the external terminal and the internal terminal. In the package structure of a semiconductor device having a semiconductor element mount interposer,
An internal terminal for connection to an external terminal of a semiconductor element mounting interposer mounted on the upper surface, an external terminal for connection to a mounting board, and a conductor wiring for electrically connecting the external terminal and the internal terminal And a package substrate formed with
The interposer is formed in a bowl shape having a substantially rectangular shape, and the external terminals are arranged at a peripheral portion, and the external terminals of the semiconductor element mount interposer and the internal terminals of the package substrate are connected via wires. A package structure of a semiconductor device. The semiconductor element is mounted on an interposer formed with an internal terminal to which the terminal of the semiconductor element is connected, an external terminal for external connection, and a conductor wiring that electrically connects the external terminal and the internal terminal. In the package structure of a semiconductor device provided with a plurality of semiconductor element mount interposers,
A slot portion having an internal terminal into which a peripheral portion of the interposer is inserted and an external terminal of the interposer is electrically connected; an external terminal for connection to a mounting board; and the external terminal and the inside of the slot portion A package substrate on which a conductor wiring for electrically connecting terminals is formed;
The interposer has a base material made of a flexible electrical insulator, a bowl shape is substantially rectangular, and the external terminals are arranged on a peripheral portion. The external terminals of each interposer are connected to the slot portions. A package structure of a semiconductor device, wherein the package structure is electrically connected to an internal terminal.   The functional layer having a thermal characteristic or a mechanical characteristic different from that of the base material of the interposer or the molding material around the base material is provided between the layers of the semiconductor element mount interposers arranged in a stacked manner. 4. A package structure of a semiconductor device according to 1 or 3.   A functional layer having a thermal property or a mechanical property different from that of the base material of the interposer, the package substrate, or the mold material around the interposer and the package substrate, between the semiconductor element mount interposer and the package substrate. The package structure for a semiconductor device according to claim 2, wherein the package structure is provided.   The functional layer is provided between two or more layers, and the plurality of functional layers include a plurality of types of functional layers having different thermal characteristics or mechanical characteristics. A package structure of the semiconductor device described. An internal terminal to which the terminal of the semiconductor element is connected, an external terminal for external connection, and a conductor wiring that electrically connects the external terminal and the internal terminal are formed, and the base material is flexible Comprising a semiconductor element mounted interposer by mounting a semiconductor element on an interposer in which the outer terminal is arranged on the peripheral edge and the bowl shape is substantially rectangular.
Packaging a semiconductor device characterized in that a plurality of the semiconductor element mount interposers are stacked and integrated by joining the external terminals without providing a terminal member for separating adjacent interposers on the surface of the external terminals. Method. An internal terminal to which a terminal of the semiconductor element is connected, an external terminal for external connection, and a conductor wiring that electrically connects the external terminal and the internal terminal are formed, and the base material is flexible A semiconductor element is mounted on an interposer made of an electrical insulator and having a bowl shape that is substantially rectangular and the outer terminals are arranged on the periphery.
An internal terminal to which an external terminal of the interposer mounted on the upper surface is connected, an external terminal for connection to a mounting board, and a conductor wiring that electrically connects the external terminal and the internal terminal are formed. A semiconductor device characterized in that the external terminal is joined to the internal terminal of the package substrate without providing a terminal member for separating the semiconductor element mounting interposer and the package substrate from the external terminal of the interposer. Packaging method. An internal terminal to which a terminal of the semiconductor element is connected, an external terminal for external connection, and a conductor wiring that electrically connects the external terminal and the internal terminal are formed, and the base material is flexible A semiconductor element is mounted on an interposer made of an electrical insulator and having a bowl shape that is substantially rectangular and the outer terminals are arranged on the periphery.
A slot portion having an internal terminal into which a peripheral portion of the interposer is inserted and an external terminal of the interposer is electrically connected; an external terminal for connection to a mounting board; and the external terminal and the inside of the slot portion A method of packaging a semiconductor device, wherein an external terminal of the interposer is electrically connected to the slot of a package substrate in which a conductor wiring that is electrically connected to the terminal is formed.

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