TW200425384A - Wafer carrier having improved processing characteristics - Google Patents

Abstract

A wafer carrier for supporting a plurality of wafers, including a plurality of slots provided in a cradle, the cradle being formed of silicon carbide and having an oxide layer overlying the silicon carbide.

Description

200425384 发明 Description of the invention: [Technical field to which the invention belongs] The present invention generally relates to fumigation equipment, and more specifically to a wafer for supporting a wafer to undergo processing such as exposure to a high temperature processing operation Carrier. In addition, the present invention relates to the use of such wafer carriers for wafer processing. [Previous Technology] It is understood in this technology that semiconductor processes generally employ workpieces to support and / or transport semiconductor wafers in various processing steps including high-temperature processes (including annealing chemical π-phase deposition, oxidation, and others). In this regard, horizontal and vertical wafer carriers (also known as wafer boats in this technology) are used to support a plurality of wafers, which are generally separated from each other at a constant pitch to form a wafer array . In this regard, the exposure of the wafer to a processing operation is generally referred to as "batch processing," in which multiple wafers are processed simultaneously.

Reduction in Ik critical crystal size, die size, and integrated circuit size The direct control of wafers processed has been increasing. For example, the industry has moved from 4-inch wafers to 6-inch wafers, and now generally uses 8-inch wafers. Further, a 12-inch (300 mm) semiconductor manufacturing plant (fabrication plant; fab) also appeared online. With the introduction of increased wafer sizes, new engineering issues arise at many stages of the manufacturing process. Further, semiconductor wafers mainly composed of silicon are being used to form traditional integrated circuit structures including logic and memory devices, and are also used to form optoelectronic devices such as waveguide multiplexers and micro-electromechanical systems (MEMS) ). In this regard, device fabrication sometimes uses an extended oxidation

O: \ 91 \ 91516.DOC -6- 200425384 step, in which the semiconductor wafers are oxidized, and sometimes the extended time k J exceeds the time period commonly encountered in traditional semiconductor processing. For example, one wafer is often exposed to one processing operation at a time, such as on a scale of five to ten days. As mentioned above, such processing operations often include oxidation of such wafers. In view of the increased processing time and the increased wafer size, technical problems have arisen that affect the robustness and quality of these devices. In this regard, the inventors have encountered defects in the wafers after undergoing such processing operations, such as partial or even catastrophic fragmentation of the wafers. Other defects include wafer deformation and notches around the outer perimeter, especially when contacting the ^ Wh U ^. 0, such as the bottom support portion of the wafer carrier in the case of a horizontal wafer boat. In this technology, it is necessary to improve the wafer carrier or boat (specifically, round carrier), and to provide improved processing operations to improve device yield and low defect rate. [Summary of the Invention] According to one aspect of the present invention, a wafer carrier is provided for supporting a plurality of Y4 round carriers including a plurality of slots provided in a bracket, the bracket containing a carbon cut and having a cover. The carbon cuts-the oxide layer. According to the aspect t of the present invention, a wafer carrier having a plurality of slots is provided. The plurality of slots have a negative visibility. In particular, the fraction of each groove has a width of ㈤ 'where WS is not less than Utw and tw is one of the thicknesses of the crystal circles. According to another feature of the present invention, a method for supporting a plurality of wafers is provided.

O: \ 91 \ 91516.DOC 200425384 B-round carrier, the wafers have a radius, and the wafer carrier includes a plurality of slots for supporting the wafers, at least a portion of each slot has A radius of curvature rs, this radius is not less than about 1.15 rw. According to a variation of this aspect of the invention, the dagger may have a negative value and a positive value. According to another aspect of the present invention, a method for processing a plurality of wafers is provided. In the method, a plurality of wafers are loaded on a wafer carrier having any one or all of the above characteristics, and the wafers are loaded on The wafer carrier is subjected to a processing operation. The processing operation may be one in which the wafers are exposed to an oxidation environment to oxidize the wafers. [Embodiment] According to a specific embodiment of the present invention, a specific wafer carrier is provided for supporting a plurality of wafers. In this regard, attention should be paid to the drawing, which illustrates a perspective view of a wafer carrier according to a specific embodiment of the present invention. As shown in the figure, the wafer carrier includes a bracket 2 which has a generally open structure and includes a plurality of bracket arms 3 having a generally arcuate shape, and the bracket arms and A plurality of support members are integrated to support such a circle. In particular, first, second and third support members 10, and 14 are provided, each of which protrudes inwardly, and a plurality of grooves 16 are provided along these members. Each slot 16 is positioned and oriented such that it is positioned along the same arc of a fixed radius to support a single individual wafer. Each slot is composed of first, second, and third slot sections 18, 20, and 22, respectively, and each slot is positioned along the first, second, and third support members 10, 12, and 14, respectively. As shown by taxi Θ 2, & provides a cross-sectional view illustrating the orientation of the wafer 30 which is spitted onto the wafer carrier 1. One of the wafer carriers illustrated in Figures 1 and 2

O: \ 91 \ 91516.DOC 200425384 is generally oriented horizontally and is the orientation of the wafer carrier in use (specifically, in a semiconductor factory environment). As illustrated, the carrier support is typically a wafer in an upright, vertical position. As clearly shown in Figure 1, the slots 6 are arranged as a linear array and are spaced from each other at a constant pitch. For example, it is shown that the second groove sections 20 are spaced from each other at a constant pitch and are in an array pattern. In this way, the carrier linearly holds the wafers to form a horizontal wafer stack. The distance between the grooves and correspondingly, the 3 4 aa circle distance can vary depending on the particular application, but is generally in the range of about 2 to about 4 mm, nominally about 2.38 mm. As shown in FIG. 2, the first, second, and third support members 10, 12, and 14 are positioned along an arc 32 having a radius equal to the wafer and a radius, so that the first The second, third and third support members are positioned along the arc 32 in sequence and the second support member is positioned circumferentially between the first and third support members 10, 14. In this regard, it is intended that the second support member is placed at a bottom-most position, that is, at the six o'clock position, so the second support member generally supports a larger portion of the weight of the wafer. The lone 32 is swept by an angle not greater than 180 degrees to assist in loading the wafers. Generally, the support portions are positioned to define an arc 32 that is not greater than about 150 degrees or-generally not greater than about 130 degrees. The official figures 1 and 2 show three support members, but the wafer carrier may have a different number of support members. For example, the second support member may be double-forked to form two different support members having different groove sections. In this case, the support members may be equally spaced from the bottom six o'clock position. As mentioned above, the wafer carrier has a generally open

O: \ 91 \ 91516.DOC 200425384 / You provide several advantages detailed below. In general, the window defined between ^ HI et al. # 3 and the optional components provides at least 4_ open areas along one of the bracket's outer part® column surfaces. In general, the open area section is at about 5G%. This open material of the wafer carrier is advantageous in that the gas flowing around the wafer carrier during the pre-oxidation step forms an equiangular, relatively uniform oxide layer. Now let ’s talk about the material of the wafer. As mentioned above, the bracket is composed of carbon and stone. According to a specific embodiment, the carbon cut contains a recrystallized slope fossil eve 'which is a material known in the art. Generally, half ¥ body grade ★ cut powder _, green body and sintering aids and binders. One of the organic binders molded, dried, heated to burn out and heat treated to densify and recrystallize the green body. The subsequent maleation and processing steps can be used to reach the final size of the wafer carrier. Other forms of carbides can be used instead of or in combination with recrystallized silicon carbide. For example, the silicon carbide substrate can be converted into a silicon carbide substrate by a conversion process, wherein the carbon preform is converted into silicon carbide by a gas phase or liquid phase technique. Generally, in this case, the preform is formed of a carbonaceous material, such as semiconductor-grade graphite. Further, in the case where a porous silicon carbide is used as a base material of the wafer carrier, the carrier may be filled with silicon. This type of combination feature is called Si_Sic or Silicon Carbide. In this regard, after a relatively porous silicon carbide substrate is formed, the substrate is then filled with molten silicon to densify the structure to a degree suitable for refractory applications (for example, in a semiconductor processing environment). The siliconized silicon carbide can be coated with a further silicon carbide layer, such as chemical vapor deposition (chemical v 邛 μ

O: \ 91 \ 91516.DOC 200425384 deposited; CVD) silicon carbide. Further, the wafer carrier may be formed of free-standing SiC, and the free-standing Sic is formed by CVD. In this case, an extended cvD procedure is performed to form the wafer carrier by itself. An oxide layer is provided to cover the silicon carbide of the wafer carrier. The oxide layer may be formed by oxidation of the support in an oxidizing environment, for example, by oxidizing the support at an elevated temperature in an oxygen-containing environment, the elevated temperature being, for example, between 950 and about It is in the range of 1300 degrees Celsius, and more generally in the range of about 1000 to about 1250 degrees Celsius. Oxidation can be carried out in a dry or humid atmosphere and is generally carried out under atmospheric pressure. A humid environment can be created by introducing steam and used to increase the oxidation rate and improve the density of the oxide layer. In this regard, U5 (wet oxidation of rc can take a grade of about ^ to "hours to form a strong and thick (such as about 2 to 3 microns) oxide layer. On the other hand, such a layer can take a grade of 5 days, For example, from 10 to 20 days, it is used to form an oxide layer based on dry oxidation treatment. Although the oxide layer is generally formed by oxidation, the oxide layer can also be deposited (for example, through a thorough-body reaction) . But 'for durability and robustness, it is preferably a thermal growth layer. 2. The silicon oxide layer is an intermediate layer (for example, as in the case of being filled with silicon, the oxide layer is silicon carbide, generally SiO, The silicon carbide of the round carrier is in direct contact. Alternatively, silicon) may exist between the silicon carbide and the covering oxide layer, as in the case of silicon carbide. The growth curve of the oxide layer, which is in accordance with the general For FIG. 3, a functional relationship with the growth time on the silicon carbide wafer carrier is illustrated.

O: \ 9U91516.DOC -11-200425384 Parabolic-growth curve to grow. For reasons discussed below, according to a specific embodiment of the present invention, the oxide layer has a thickness that exceeds one of the relatively faster growing portions of the curve. For example, the oxide layer may have a thickness greater than about 0.5 micrometers, or specifically greater than about 0.75 micrometers, such as greater than about 1. G micrometers, and even 15 micrometers. According to a particular embodiment of the present invention ', the oxide has a thickness of at least 2 microns, for example, on the order of about 2 to about 3 microns. It should be noted that the oxide layer according to a specific embodiment of the present invention is a layer provided on the wafer carrier, as opposed to any native oxide that may be present on the wafer carrier, but its thickness is relatively low. Further, although the above oxide layer is generally formed by a thermal oxidation technique, other techniques such as direct deposition of an oxide layer may also be used. It has been found that the formation of an oxide layer (e.g., by a thermal pre-oxidation step) overrides process control in a semiconductor factory environment. In particular, the inventors have discovered that during the traditional oxidation process of forming a relatively thick oxide layer on the crystals, the wafers often pass through the growth of the oxide layer on the wafers and / or An oxide layer formed on the wafer carrier is adhered to the wafer carrier. During the subsequent cooling of the wafer / wafer carrier assembly, the difference in shrinkage and thermal expansion coefficient between the wafer and the carrier may cause stress in the wafers. The difference in & like thermal expansion / contraction characteristics can be caused by the combination and structure difference, and can eventually cause damage to these wafers. At the end, under the condition, these wafers can be inflammable due to the cracking mechanism, so early. Incorporating a pre-oxidation step to form an oxide layer on the carrier, thereby reducing the growth of the oxide layer on the carrier during the heat treatment of the wafers' and reducing the Increasing adhesion tendency

O: \ 91 \ 91516.DOC -12- 200425384 Strong program control and wafer yield. According to another feature of the present invention, the groove in the wafer carrier has a specific radius of curvature rs, which further enhances program control and wafer yield, specifically during the above-mentioned high temperature processing. As shown in FIG. 2, the wafer has a nominal radius. Current state-of-the-art wafer fabs use 8-inch wafers and are increasingly using 12-inch (300 mm diameter) wafers. Therefore, although older plants can use smaller wafers and newer generation plants use larger wafers, the new plant can use one wafer with a grade of about 15G mm-radius ^. According to a specific feature of a specific embodiment, the curvature radius of the groove is not less than about 115 mm. In other words, the radius of curvature of the groove used to support the wafer is larger than the radius of the wafers. Looking at FIG. 4 now, it is shown that 1 is approximately twice as large. Even further-the curvature of the slot can be close to a straight line (rs == infinity). This particular embodiment is illustrated in FIG. 5. In this case, the portion of the 'groove' that contacts the wafer extends in a straight line. The radius of the progressive groove curvature may have the opposite orientation, i.e. the radius of the crystal circle of the fish ^ has a negative radius of curvature. This is shown in Figure 6, where the groove has a generally convex-shape and has a -radius that extends from the point of contact between the wafer and _ in a direction opposite to the day-to-day® radius . In the foregoing specific embodiments, the curvature radii are the same. As a matter of fact, the second mother-groove section has the same characteristics as the above-mentioned radius at least in part along the second groove area of the second support member.

O: \ 91 \ 91516.DOC -13- 200425384 The minimization of the potential oxidative adhesion area between the wafer and the carrier is provided by providing a groove portion having the above-curvature half #rs. In this way, an oxide-to-oxide bond is formed between the wafer and the carrier, and the adhesion is minimized: the surface is weaker and more likely to break during processing (for example, during cooling), thereby weakening the surface. The thermal stress in the wafer that caused the above fragmentation. According to another specific embodiment of this Meming, at least a part of the grooves of the wafer carrier has a width WS greater than a thickness of one of the wafers. Specific +, the width is generally not less than l3Gtw. According to the implementation of another item, WS is not less than 1.35 tw and may be in the range of about i 35 tw to about i 50. In this regard 'FIG. 7 illustrates the groove width Ws (not shown in scale) relative to the wafer thickness ~. It should be noted that the actual thickness W of such wafers may vary depending on the wafer brand, the intended use, the wafer diameter, and the composition (eg, SOI). However, the wafer generally has a thickness in the range of about 0 45 mm to about 0.80 mm, and more generally is between about 0.50 to about 0.765 mm. By providing the above relative widths to the grooves, the narrower widths such as /, /, such as 1 · 10, to 1.25 tw, and the formation of relatively thick oxide layers are assisted by the extra space in the grooves. In addition, by weakening the degree to which wafers are constrained within the trenches during oxide growth, circular latent becomes less problematic. In this regard, using traditional techniques, the confinement of the circle in the groove often causes the wafer to creep at high temperatures and create a gap. The formation of a notch in the wafer around the outer periphery often forms an unfavorable mechanical interlocking structure. In particular, due to the different thermal shrinkage characteristics of the wafer and the wafer carrier, once the notch is cooled, the notch often engages the groove and causes mechanical stress in the wafer.

O: \ 91 \ 9I516.DOC -14 · 200425384 In addition to the specific features of the specific embodiment of the sa circular carrier described above, the present invention = provides processing of a plurality of wafers, which is called batch processing. In this regard, a round carrier carries a plurality of wafers, which are generally arranged at a constant pitch as a linear array. The wafer / wafer carrier assembly is then placed in a furnace (e.g., a processing tube) for high temperature processing. As mentioned above, an ideal processing insert is formed on these wafers—a relatively thick oxide layer—which is particularly suitable for MEMS and optoelectronic applications. The specific embodiments of the present invention have been specifically described above, but it should be understood that various modifications can be made without departing from the scope of the patent scope of this application. [Brief description of the drawings] ~ The present invention can be better understood by referring to the accompanying drawings, and those skilled in the art will better understand its many purposes, features and advantages. FIG. 1 is a perspective view of a horizontal wafer carrier according to a specific embodiment of the present invention. FIG. 2 is a cross-sectional view of a horizontal wafer carrier carrying a wafer according to a specific embodiment of the present invention. Figure 3 is a graph illustrating the oxide growth curve on a carbon-cut wafer carrier. FIG. 7 shows a radius of curvature of a groove of a semiconductor wafer according to a specific embodiment of the present invention. Fig. 5 shows the curvature radius of a groove of a semiconductor crystal circle according to another embodiment of the present invention. Fig. 6 shows the curvature radius of a groove of a semiconductor crystal circle according to another specific example of a yoke according to the present invention.

O: \ 91 \ 91516.DOC 200425384 FIG. 7 shows the thickness of the cross section of a wafer in a groove according to a specific embodiment of the present invention, which is opposite to the width of the groove. The use of the same reference symbols in different drawings indicates similar or identical items. [Illustration of representative symbols] 1 wafer carrier 2 bracket 3 bracket arm 10 first support member 12 second support member 14 third support member 16 slot 18 first slot section 20 second slot section 22 third Slot section 30 wafer 32 arc O: \ 91 \ 91516.DOC -16-

Claims (1)

200425384 Patent application park: 1. 2. 3. 4. A wafer carrier for supporting a plurality of wafers, comprising: a plurality of slots provided in a bracket, the bracket containing silicon carbide And has an oxide layer covering the carbonized stone. Such as the scope of patent application! The item of the wafer carrier, wherein the carrier is crystalline silicon carbide. ^ As for the wafer carrier in the scope of the patent application, the bracket in # contains silicon carbide filled with silicon. / A The wafer carrier according to item i of the patent application scope, wherein the bracket contains a chemical-resistant fossil eve. 5. The wafer carrier according to item 1 of the patent application scope, wherein the carrier-type CVD SiC. Including independence 6. Such as the scope of patent application! The wafer carrier according to item 1, wherein the oxide layer comprises silicon oxide 7. The wafer carrier according to item 6 of the patent application scope, wherein the silicon oxide has a thickness of about 0.5 micrometer. 8. The wafer carrier according to item 6 of the patent application, wherein the oxygen is cut to a thickness of about 0.75 microns. 9. The wafer carrier as claimed in claim 6 wherein the oxidation is greater than a thickness of about 1.0 micron. H). The wafer carrier according to item 6 of the patent application scope, wherein the thickness is about one and a half microns. 7 / You have U. For example, the wafer carrier in the scope of patent application item i, in which the oxide layer is grown by growth. …, O: \ 91 \ 91516.DOC 200425384 12. If the wafer carrier of the first scope of the patent application, the oxide layer is deposited. For example, the wafer carrier of item 丨 of the patent scope is declared, wherein the wafer carrier is a horizontal wafer carrier, which is used to support a wafer which is generally oriented in an upright and vertical position. For example, the wafer carrier of item i of the patent scope is declared, wherein the grooves are configured as a linear array and spaced from each other at a constant pitch. H-wafer carrier for supporting a plurality of wafers, the wafers have a thick ftw ', the wafer carrier includes a plurality of slots for supporting the wafer array, and part of the wafer carrier has One slot width ws, # 中 ws is not less than about 1.30 tw. 16. If the wafer carrier for the scope of patent application No. 15 is, the ws is not less than about CD 17. If the wafer carrier for the scope of patent application No. 15 is within the range of about 1.50 tw. = Wafer carrier for item i of the patent scope, where the bracket includes to the support, each component is provided to support and interface only 4 yen, and the female slot has the first and second parts extending along the first and part, respectively. First, second and third slot sections. -And the second branch, 19. The wafer carrier of item 18 in the scope of patent application, wherein the first and third groove sections have -radius equal to the wafers with a radius of: half :: brother · arc and Positioning, and Xi Sheng Dang ... Circle of + diameter of--and the first, second, and third branches of the 5th Hai are positioned so that the second support 0… positioned along the circumference between the components. Special brother 1 and the third name 20. The wafer carrier of item 19 of the patent application scope, wherein each slot has an O: \ 91 \ 91516.DOC 200425384 part of the slot width WS including the second slot At least part of a segment. 21. The wafer carrier according to item 19 of the patent application scope, wherein the first, second and third groove sections are spaced along the arc not more than 180 degrees. 22. The wafer carrier as claimed in claim 19, wherein the first, second and third groove sections are spaced along the arc of not more than 150 degrees. 23.-A wafer carrier for supporting a plurality of wafers, the wafers having a radius \ The wafer carrier includes a plurality of slots for supporting the plurality of wafers, and at least the mother-slot- The part has a radius of curvature q, where L is not less than about 1.1 5 rw. 24. If the wafer carrier under the scope of the patent application item 23 is applied, in which "less than about 1_25 rw. 25. If the wafer carrier under the scope of the patent application item 23 is applied, L is not less than approximately 1.35 rw. The wafer carrier of item 23, wherein "less than about 1.50 rw 〇27. As in the wafer carrier of claim 23, wherein ^ is infinite, and at least a portion of each slot extends along a straight line. 28. A crystal cap for supporting a plurality of wafers, the wafers having a radius of ^, the wafer carrier comprising at least-a portion having a -curvature hemicenter for supporting each slot of the wafer, wherein ^ Has a negative value and rw has a positive value. 29 · —A method for processing a plurality of wafers, comprising: loading a plurality of wafers into a wafer carrier, the wafer carrier including a plurality of slots provided in a tray, the tray containing Silicon carbide and has an oxide layer covering the O: \ 91 \ 91516.DOC 200425384 silicon carbide; and At least a part of each groove has a circle, and a delta wafer has a radius of a plurality of grooves such as a plurality of wafers having a curvature radius rs, where rs is not less than about 1.15 rw; and The circle is subjected to a processing operation. 33 · —A method for processing a plurality of wafers, comprising: · loading a plurality of wafers into a wafer carrier, the wafers having a thickness tw ', the wafer carrier including a substrate for supporting the wafer A plurality of grooves of the circular array, at least a portion of each groove having a groove width Ws, wherein% is not less than about 丨 30 tw; and subjecting the wafers to a processing operation. 34 · —A wafer carrier for supporting a plurality of wafers, the wafers having a thickness tw and a radius rw, the wafer carrier comprising a plurality of slots for the plurality of wafers of a branch building, each At least a part of a slot has a slot width Ws and a radius of curvature rs, where Ws is not less than about ι · 30tw and rs is not less than about 1.15 rw, the wafer carrier further includes silicon carbide and covers the silicon carbide An oxide layer. O: \ 91 \ 91516.DOC -4-