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TW200411854A - Semiconductor chip package and method for the same - Google Patents

Semiconductor chip package and method for the same Download PDF

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Publication number
TW200411854A
TW200411854A TW091137974A TW91137974A TW200411854A TW 200411854 A TW200411854 A TW 200411854A TW 091137974 A TW091137974 A TW 091137974A TW 91137974 A TW91137974 A TW 91137974A TW 200411854 A TW200411854 A TW 200411854A
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TW
Taiwan
Prior art keywords
substrate
stiffening member
wafer
item
patent application
Prior art date
Application number
TW091137974A
Other languages
Chinese (zh)
Other versions
TWI239080B (en
Inventor
Su Tao
Kuang-Lin Lo
Tsung-Sheng Lee
Yaw-Yuh Yang
Yuan-Kai Tao
Original Assignee
Advanced Semiconductor Eng
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Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW091137974A priority Critical patent/TWI239080B/en
Priority to US10/605,034 priority patent/US20040124515A1/en
Publication of TW200411854A publication Critical patent/TW200411854A/en
Application granted granted Critical
Publication of TWI239080B publication Critical patent/TWI239080B/en
Priority to US11/613,195 priority patent/US20070087480A1/en

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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)

Abstract

A method for manufacturing semiconductor chip packages includes the following steps. First, a substrate is provided. Subsequently, many chips are assembled onto the substrate and are electrically connected therewith. Next, a stiffener is assembled onto the substrate and the stiffener has a top surface and a bottom surface facing the substrate. Next, a molding compound is formed to cover the semiconductor chip, the substrate, the top surface of the stiffener and the bottom surface of the stiffener. Afterwards, the molding compound, the substrate and the stiffener are cut for performing a singulation step.

Description

200411854 五、發明說明（1) 發明所屬之技術 本發明是有關於一籀a ΰ & # ^ 別是有關於-種她封二封/結構及其製程，且= 其所對應之製程。 a體趣曲程度之晶片封裝結構及 先前技術 ' 在半導體產業中，積體電路（Integrated Circults， 1C)的生產，主要分為三個階段：裸晶片（die)的製造、積 體電路(IC)的製作以及積體電路(1C)的封裝(Package) 等。其中，裸晶片係經由晶圓（Wafer)製作、電路設計、 光罩製作以及切割晶圓等步驟而完成，而每一顆由晶圓切 剎所形成的稞晶片，經由裸晶片上之焊墊（B〇nding pad) 與外部訊號電性連接後，再以封膠材料將裸晶片包覆著， 其封裝之目的在於防止裸晶片受到濕氣、熱量、雜訊的影 響，並提供稞晶片與外部電路，比如與印刷電路板 (Printed Circuit Board，PCB)或其他封裝用基板之間電 性連接的媒介，如此即完成積體電路的封裝（Packa 驟。 在現今的電子產品中一般均朝向輕、薄、短、小的 趨勢發展’尤其是攜帶式的電子產品，因此在半導體封裝 技術上’亦開發出許多小型晶片封裝結構，比如是晶片^ 寸構裝（Chip Scale Package，CSP)、迷你球格陣列封裝 (mini-BGA)或微型球格陣列封裝（micr〇-BGA)等。就迷^ 球格陣列封裝而言，係先將多個晶片以其背面黏貼到基』板 上’並利用打線的方式使晶片與基板電性連接，接著再灌200411854 V. Description of the invention (1) The technology to which the invention belongs The present invention is related to a 籀 a ΰ &# ^ In addition, it is related to a kind of hermetic seal / structure and its process, and = its corresponding process. A chip packaging structure and previous technology of the body fun degree In the semiconductor industry, the production of integrated circuits (1C) is mainly divided into three stages: the production of bare chips (die), and the integrated circuit (IC) ), And the package of the integrated circuit (1C). Among them, bare wafers are completed through wafer (wafer) production, circuit design, photomask fabrication, and wafer dicing, and each plutonium wafer formed by the wafer cutting brake passes through the pads on the bare wafer. (Bonding pad) After being electrically connected to the external signal, the bare chip is covered with a sealing material. The purpose of the package is to prevent the bare chip from being affected by moisture, heat, and noise, and to provide the chip and the An external circuit, such as a medium that is electrically connected to a printed circuit board (PCB) or other packaging substrates, completes the packaging of integrated circuits (Packa steps. In today's electronic products, they are generally lighter. Development of thin, short, short and small 'especially for portable electronic products, so in semiconductor packaging technology', many small chip packaging structures have also been developed, such as chip scale package (CSP), mini Ball grid array package (mini-BGA) or micro ball grid array package (micr0-BGA), etc. As for the ball grid array package, multiple chips are first adhered to the substrate with their backsides. ’And use a wire bonding method to electrically connect the chip to the substrate, and then refill

10231twf.ptd 第7頁 200411854 五、發明說明（2) ___^ 5 3 i —同時包覆多個晶片及基板，之後再利用切％的 =式進仃早切的步驟，以形成多個晶片封裝體。因^的 ,球袼陣列封裝中，每一晶片封裝體之封裝上 貝㈢等於基板的面積，故可以提高封裝積集度，^亦、的 ^面積相對於基板面積的比例可以大幅提高，以符二：晶 迷你球格陣丄：的。另夕卜，就製程上·而言， 被廣泛地應用在半導體封裝領域中。 门口此 球格圖’其中第1^繪示習知迷你 迷你球格的上視示意圖，第1Β圖綠示習知 球格陣列tn :刀害;，後的剖面示意_。-般就迷你 固定到一，係將多個晶片130以矩陣排列的方式. 接。之德^ 上，並藉由打線的方式與基板1 1 〇電性連 之凹穴蓋到一封膠製程，其係先將一模具(未緣示) 後再灌入一二穿在凹穴中會容納多個晶片130，然 17〇可以包覆二到f具之凹穴中’使得封裝材料 以完成多個曰日片二，線180 ’如此-道封膠製程便可 裝體!02均二=102之封膠作業，其中每-晶片封 來，便進杆Λ 、晶片130及封裝材料170。接下 分離。 。的製程，使得每一晶片封裴體1 0 2可以被 應力，使得曰在Η進/丁切割製程時，每一晶片封裝體102因受 甚薄時，1 ^ a ^裝體1 Q2會產生翹曲的現象，當基板110 〜曲的現象更為嚴重，如第2B圖所示。此時若10231twf.ptd Page 7 200411854 V. Description of the invention (2) ___ ^ 5 3 i — cover multiple wafers and substrates at the same time, and then use the %% = type to enter the early cutting step to form multiple chip packages body. Because, in the ball array array package, the package size of each chip package is equal to the area of the substrate, so the package accumulation degree can be improved, and the ratio of the area to the area of the substrate can be greatly increased. Symbol II: Crystal Mini Ball Lattice 丄: Yes. In addition, in terms of manufacturing process, it is widely used in the field of semiconductor packaging. At the entrance of this ball grid chart, where 1 ^ shows the top view of the conventional mini ball grid, and Figure 1B shows the conventional ball grid array tn: knife damage; -Generally, the mini is fixed to one, and the multiple chips 130 are arranged in a matrix. The method is to cover the cavity of the substrate 1 1 0 by wire bonding to a plastic process, which involves pouring a mold (not shown) and then pouring one or two into the cavity. The center will accommodate multiple wafers 130, but 170 can cover two to the cavity of the tool, so that the packaging material can complete multiple Japanese and Japanese films. The line 180 is so-the sealing process can be installed! 02 Even two = 102 sealing operations, where each-the chip is sealed, then enter the rod Λ, the chip 130 and the packaging material 170. Separated. . Process, so that each wafer package body 102 can be stressed, so that during the advancement / cutting process, when each wafer package 102 is very thin, 1 ^ a ^ package 1 Q2 will produce The warping phenomenon is more serious when the substrate 110 is bent, as shown in FIG. 2B. If

l〇231twf.ptd 第8頁 200411854 五、發明說明（3) 將晶片封裝體102裝配到一母板（未繪示）上時，基板11〇邊 緣位置相距母板之間的距離係大於基板丨丨〇中間位置相距 母板之間的距離’因此位在基板丨丨0邊緣位置的焊球丨8 2與 母板接合後，在經過多次熱循環的操作下，常會有破裂或 剝離的現象。 發明内交 有鑑於此，本發明的一目的是提出一 檀晶片封裝結 構及其製程，可以大幅降低基板之翹曲程度 本發明的另一目的是提出一種晶片封裝結構及其製 程’可以大幅提昇基板與母板間的接合可靠度。 神在敘述本發明之前，先對空間介詞的用法做界定， 所明空間介詞"上”係指兩物之空間關係係為可接觸或不可 接觸均可。舉例而言’A物在8物上’其所表達的意思係為 A物可以直接配置在B物上，A物有與b物接觸；或者a物 配置在β物上的空間中，A物沒有與B物接觸。 首先要為接達供本發二之上述㈣’提出一種晶片封裂製程， 百先要k供一基板。接著，要配設多個晶片於美， 晶片與基板電性連接。缺後，還要配μ _ ^ 上，且加勁構件具有一= ;面=向ί板L接…還要形成—封裝材料以包覆晶 片基板、加勁構件之頂面及加勁構件之 切割封裝材料、基板及加勁構件。 之後要 口，本/虛明之曰一較佳實施例’加勁構件具有多個開 子w於Β曰片配置在基板上的位置，而依照本發l〇231twf.ptd Page 8 200411854 V. Description of the invention (3) When the chip package 102 is assembled on a mother board (not shown), the distance between the edge position of the substrate 11 and the mother board is greater than the substrate 丨丨 〇 The distance between the middle position and the motherboard 'so the substrate is located at the edge of the substrate 丨 8 The solder ball is bonded to the motherboard, and it often cracks or peels after multiple thermal cycling operations . In view of this, an object of the present invention is to propose a chip packaging structure and a manufacturing process thereof, which can greatly reduce the degree of warpage of the substrate. Another object of the present invention is to propose a chip packaging structure and a manufacturing process thereof, which can greatly improve Reliability of bonding between substrate and motherboard. Before describing the present invention, God first defined the use of space prepositions. The space preposition "quote" means that the spatial relationship between the two things is accessible or inaccessible. For example, 'A 物 在 8 物' The meaning of the above is that the A object can be directly disposed on the B object, and the A object is in contact with the b object; or the a object is disposed in the space on the β object, and the A object is not in contact with the B object. First of all, The above mentioned method for the second issue of the present invention proposes a wafer sealing process. One hundred substrates must be provided for one substrate. Next, multiple wafers must be provided in the United States, and the wafers are electrically connected to the substrate. _ ^ Above, and the stiffening member has a =; surface = connected to the plate L, but also formed-packaging material to cover the wafer substrate, the top surface of the stiffening member and the cutting packaging material, substrate and stiffening member of the stiffening member. Important point, a preferred embodiment of this / Xu Mingzhi 'stiffening member has a plurality of openings at the position where the B film is arranged on the substrate, and according to the present invention

200411854200411854

:之實施例’加勁構件之底面係朝向晶片。另 二月曰，構:：以藉由一黏著材料與基板接合。此外，在 日日=土基板及加勁構件之後，還要形成多個焊球於基 個r玻ίΐί切割晶片、基板及加勁構件之前，要形成多 #I二对上。另外，在配設晶片於基板上時，晶片係 貼附於基板上’1還進行-打線製程以形 t夕條V線電性連接晶片與基板。而加勁構件的材質比 是銅。 综上所述，本發明之晶> 加勁構件具有較高之勁度，因 在基板係為甚薄的狀態下，比 間，藉由加勁構件可以大幅縮 而使得基板之下表面係呈現較 裝體裝配到一母板上時，基板 離與基板中間位置相距母板之 小，因此位在基板邊緣位置的 經過多次熱循環的操作下，亦 現象’且可以大幅提高基板與 為讓本發明之上述目的 懂’下文特舉一較佳實施例， 明如下： 實施方i t封裝結構及其製程，由於 此在進行切割製程時，尤其 如約為0 · 1公釐到0 . 5公釐之 減晶片封裝體之魅曲程度， 為平整的狀態。故當晶片封 邊緣位置相距母板之間的距 間的距離之間的差距會縮 焊球在與母板接合後，即使 可以避免產生破裂或剝離的 母板間接合的可靠度。 1特徵、和優點能更明顯易 並配合所附圖式，作詳細說 請參照第2圖至第8圖，其繪示依照本發明第一較佳 貝施例之一種迷你球格陣列封裝製程之剖面放大承意圖。: Embodiment ′ The bottom surface of the stiffening member faces the wafer. Another February said, the structure: to join the substrate with an adhesive material. In addition, after the day = the soil substrate and the stiffening member, a plurality of solder balls must be formed before the basic glass substrate, the substrate and the stiffening member are cut, and a plurality of pairs of pairs are formed. In addition, when the wafer is arranged on the substrate, the wafer is attached to the substrate'1 and a wire bonding process is performed to electrically connect the wafer and the substrate in a V-line. The material ratio of the stiffener is copper. To sum up, the crystal of the present invention has a higher stiffness, because in the thin state of the substrate system, the stiffening member can be greatly reduced to make the lower surface of the substrate appear relatively. When the body is assembled on a mother board, the substrate is far away from the mother board in the middle position of the substrate. Therefore, it is also a phenomenon that the substrate is located at the edge of the substrate and subjected to multiple thermal cycles. The above purpose of the invention is understood as follows. A preferred embodiment is given below, which is described as follows: The implementation of the it packaging structure and its process, because of this, when the cutting process is carried out, especially such as about 0.1 mm to 0.5 mm The reduction of the degree of charm of the chip package is flat. Therefore, when the distance between the edge of the wafer package and the distance between the mother board and the mother board is reduced, the reliability of the bonding between the mother boards can be avoided even after the solder balls are bonded to the mother board. 1 Features, advantages and advantages can be more obvious and easy to match the drawings, for details, please refer to FIG. 2 to FIG. 8, which illustrate a mini ball grid array packaging process according to the first preferred embodiment of the present invention. The section enlarges the intention.

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首先，請參照第2圖，本發明之迷你球格陣 先提供一基板21〇 ’其中基板210具有—上表面 表面222，並且基板210還具有多個晶片座214、多個 216、224，其中晶片座214係以矩陣排列的方式配置在. 板2 10之上表面212上，而接點216亦位在基板21〇 土 212上且環繞在所對應之晶片座214的周圍；接點224係^己面 置在基板210之下表面222上。 接下來’還要提供多個晶片230，每一晶片23〇具有 一主動表面232及對應之一背面242，並且每一晶片23〇還 具有多個接點234，環繞在晶片230之主動表面232上的周 圍位置。而每一晶片230係以其背面242並藉由一黏著材料 244貼附在對應的基板210之晶片座214上。並且藉由打線 的方式’透過導線280可以使每一晶片230與基板210電性 連接，而導線280之一端係接合到晶片230之接點234上， 導線2 8 0之另一端係接合到基板2 1 〇之接點2 1 6上。 請參照第3圖及第3A圖，其中第3A圖繪示第3圖中加 勁構件的上視示意圖。接下來，可以利用一黏著材料29〇 將一加勁構件250貼附到基板230上，加勁構件250係類似 蓋子的結構，其係由一頂部252、一側壁部份254及一凸緣 256所構成，側壁部份254之上側254a係環繞連接於頂部 2 5 2之周緣處，並且側壁部份2 5 4係傾斜於頂部2 5 2，藉由 加勁構件250之頂部252及側壁部份254會形成一容納孔 258，可以容納多個晶片23〇。而加勁構件25〇還具有多個 開口 260，以矩陣排列的方式配置在加勁構件25〇的頂部First, please refer to FIG. 2. The mini ball grid array of the present invention first provides a substrate 21 ′, wherein the substrate 210 has an upper surface 222, and the substrate 210 further includes a plurality of wafer holders 214, a plurality of 216, and 224. The wafer holders 214 are arranged in a matrix arrangement on the upper surface 212 of the board 2 10, and the contacts 216 are also located on the substrate 212 and 212 and surround the corresponding wafer holder 214; the contacts 224 are The first surface is placed on the lower surface 222 of the substrate 210. Next, a plurality of wafers 230 are provided, each wafer 23 has an active surface 232 and a corresponding back surface 242, and each wafer 23 has a plurality of contacts 234 surrounding the active surface 232 of the wafer 230. On the surrounding location. Each wafer 230 is attached to the wafer base 214 of the corresponding substrate 210 by its back surface 242 and an adhesive material 244. And by means of wire bonding, each chip 230 can be electrically connected to the substrate 210 through the wire 280, and one end of the wire 280 is bonded to the contact 234 of the chip 230, and the other end of the wire 280 is bonded to the substrate. 2 1 〇 contact 2 16. Please refer to Fig. 3 and Fig. 3A, wherein Fig. 3A shows a schematic top view of the stiffening member in Fig. 3. Next, an adhesive material 29 can be used to attach a stiffening member 250 to the substrate 230. The stiffening member 250 is a cover-like structure, which is composed of a top portion 252, a side wall portion 254, and a flange 256. The upper side 254a of the side wall portion 254 is connected around the periphery of the top 2 5 2 and the side wall portion 2 5 4 is inclined to the top 2 5 2. The top portion 252 and the side wall portion 254 of the stiffening member 250 are formed. A receiving hole 258 can accommodate a plurality of wafers 23. The stiffening member 25 has a plurality of openings 260 and is arranged on the top of the stiffening member 25 in a matrix arrangement.

200411854 五、發明說明（6) 252 ’並且開口 260的位置係對應於晶片230配置在基板2 1〇 上的位置。凸緣2 5 6係環繞連接於側壁部份2 5 4之下側 2 5 4b，並且凸緣256係向容納孔258的外部方向延伸，而其 延伸方向係平行於頂部252，其中加勁構件25〇係以其凸緣 2 5 6與基板2 1 0接合。此外，加勁構件2 5 〇的材質比如是銅 或是其他不易撓曲的材質。 請參照第4圖，接下來進行灌模製程，首先要提供一 模具270 ’模具270具有一模穴272及一頂壓部274，頂壓部 274係位在模穴272的周圍。接著，將模具27〇頂壓到基板 2 1 0上’其中模具2 7 0係以其頂壓部2 7 4頂壓到加勁構件2 5 〇 的凸緣2 5 6上，此時模具2 5 0之模穴2 7 2會容納晶片2 3 0、導 線280及加勁構件250。接著，便灌入一封裝材料276到模 具270之模穴272中，如第5圖所示，封裝材料276會包覆晶 片2 3 0、導線2 8 0及加勁構件2 5 0，而加勁構件2 5 〇具有一頂 面262及對應之一底面264，加勁構件250之底面264係朝向 基板210，而封裝材料276係包覆加勁構件25〇之頂面262及 加勁構件250之底面264。接著，再進行冷卻、脫膜等步 驟，而形成如第6圖所示的樣式。 一接著可以利用一刀具（未繪示）來切割封裝材料276、 加勁構件250及基板210，以形成多個獨立的晶片封裝體 300，如第7圖所示，其中每一晶片封裝體3〇〇均具有基板 210、晶片230、多個導線280、加勁構件250之頂部256及 封裝材料276，其構件之間的相關位置如前所述，在此便 不再贅述。最後，再利用植球的方式，植上多個焊球282200411854 V. Description of the invention (6) 252 'and the position of the opening 260 corresponds to the position where the wafer 230 is arranged on the substrate 2 10. The flange 2 5 6 is connected to the lower side 2 5 4b of the side wall portion 2 5 4, and the flange 256 extends toward the outside of the receiving hole 258, and the extending direction is parallel to the top portion 252, of which the stiffener 25 〇 is joined to the substrate 2 10 with its flange 2 5.6. In addition, the material of the stiffening member 250 is, for example, copper or other materials that are not easily bent. Please refer to FIG. 4. Next, in the mold filling process, a mold 270 ′ is provided first. The mold 270 has a cavity 272 and a pressing portion 274, and the pressing portion 274 is located around the cavity 272. Next, the die 27 is pressed against the substrate 2 10 ', wherein the die 2 70 is pressed against the flange 2 5 6 of the stiffening member 2 5 0 with its pressing portion 2 74, and at this time the die 2 5 The cavity 2 7 2 of 0 will receive the wafer 2 3 0, the wire 280 and the stiffening member 250. Next, an encapsulating material 276 is poured into the cavity 272 of the mold 270. As shown in FIG. 5, the encapsulating material 276 will cover the wafer 2 30, the wire 2 8 0, and the stiffening member 2 50, and the stiffening member 25.0 has a top surface 262 and a corresponding bottom surface 264. The bottom surface 264 of the stiffening member 250 faces the substrate 210, and the packaging material 276 covers the top surface 262 of the stiffening member 250 and the bottom surface 264 of the stiffening member 250. Next, steps such as cooling and film release are performed to form a pattern as shown in FIG. One can then use a cutter (not shown) to cut the packaging material 276, the stiffening member 250, and the substrate 210 to form a plurality of independent chip packages 300, as shown in FIG. 7, where each chip package 3 All have a substrate 210, a wafer 230, a plurality of wires 280, a top portion 256 of the stiffening member 250, and a packaging material 276. The related positions between the components are as described above, and will not be repeated here. Finally, the method of planting balls was used to plant multiple solder balls 282

第12頁 200411854Page 12 200411854

— 在上述的貫施例中，係先進行切割的步驟，才再進 =植球的步驟，然而本發明的應用並非僅限於此，亦可以 疋先進行植球的步驟，再進行切割的步驟。請依序參照第 9圖及第8圖，其中第9圖繪示依照本發明第一較佳實施例 之另一種迷你球格陣列封裝製程之剖面放大示意圖。請先 參第9圖，在進行灌模製程之後，可以先利用植球的方 式，植上多個焊球282於基板21〇之接點224上，接著再利 用一刀具（未繪示）來切割封裝材料276、加勁構件25〇及基 板210，以形成多個獨立的晶片封裝體3〇〇，如第8圖所 示〇 於基板210之接點224上，形成如第8圖所示的結構。 一 請參照第8圖，在上述的晶片封裝體3〇〇中，由於加 勁構件2 5 0具有較高之勁度，因此在進行切割製程時，尤 其在基板2 1 0係為甚薄的狀態下，比如約為〇 · 1公釐到〇. $ 公釐之間，藉由加勁構件25〇可以大幅縮減晶片封裝體3〇q 之想t程度，而使得基板21〇之下表面222係呈現較為平整 的狀悲。故當晶片封裝體3 〇 〇裝配到一母板（未繪示）上 ^ ’基板2 1 0邊緣位置相距母板之間的距離與基板2丨〇中間 位置相距母板之間的距離之間的差距會縮小，所以位在基 板210邊緣位置的焊球282在與母板接合後，即使經過多二^ 熱循環的操作下，亦可以避免產生破裂或剝離的現象，因 而可以大幅提高基板2 1 0與母板間接合的可靠度。 在前述的較佳實施例中，加勁構件具有多個開口， 其係以矩陣排列的方式配置在加勁構件的頂部，然而本發— In the above-mentioned embodiment, the cutting step is performed first, and then the ball implantation step is performed. However, the application of the present invention is not limited to this. The ball implantation step may be performed first, and then the cutting step may be performed. . Please refer to FIG. 9 and FIG. 8 in order. FIG. 9 shows an enlarged schematic cross-sectional view of another mini ball grid array packaging process according to the first preferred embodiment of the present invention. Please refer to FIG. 9 first. After the injection molding process, a plurality of solder balls 282 can be planted on the contacts 224 of the substrate 21 and then a tool (not shown) can be used. The packaging material 276, the stiffening member 25 and the substrate 210 are cut to form a plurality of independent chip packages 300, as shown in FIG. 8, and on the contact 224 of the substrate 210, as shown in FIG. structure. Please refer to FIG. 8. In the chip package 300 described above, since the stiffening member 250 has a high stiffness, it is particularly thin when the substrate 2 10 is in a cutting process. For example, between about 0.1 mm and 0.00 mm, the stiffening member 25 can greatly reduce the desired degree of the chip package 30Q, so that the lower surface 222 of the substrate 21 appears. More flat state. Therefore, when the chip package 300 is assembled on a mother board (not shown) ^ 'the distance between the edge position of the substrate 2 1 0 and the mother board and the distance between the middle position of the substrate 2 and the mother board The gap will be reduced, so after the solder ball 282 located on the edge of the substrate 210 is bonded to the motherboard, it can avoid cracking or peeling even after more than two thermal cycle operations, so the substrate 2 can be greatly improved. 10 Reliability of joint with mother board. In the foregoing preferred embodiment, the stiffening member has a plurality of openings, which are arranged on the top of the stiffening member in a matrix arrangement. However, the present invention

10231twf.ptd 第13頁 200411854 五、發明說明（8) 明的應用並非限於此，加f ^ 1 η . 劲、、、σ構亦可以是不具開口的樣 1 ^{^ f Μ1圖所不，其繪示依照本發明第二較佳 二種迷你球格陣列封褒製程之刹面放大示意圖， ;ni貫施針的標號與第-較佳實施合卜樣者，則 ^:# λ把例中所指明的構件係雷同於在第一較佳實施 •j中斤私明的構件，在此便不再贅述。 '先茶照第1 0圖’其中加勁構件350係類似蓋子的結 #，/、係由一頂部352、一側壁部份354及一凸緣356所構 '相,彳差σ卩伤3 5 4之上側3 5 4 a係環繞連接於頂部3 5 2之周緣 处，亚且側壁部份354係傾斜於頂部352，藉由加勁構件 350之頂部352及側壁部份354會形成一容納孔358，可以容 納多個晶片230，而加勁構件350之頂部352還具有一頂面 362及對應之一底面36〇，加勁構件35〇之底面36〇係朝向晶 片230及基板210。而凸緣356係環繞連接於側壁部份354之 下側354b，並且凸緣356係向容納孔358的外部方向延伸， 而其延伸方向係平行於頂部3 5 2，其中加勁構件3 5 〇係以其 凸緣356與基板210接合，而在進行灌模時，模具"ο之頂 壓部274會頂壓到加勁構件350的凸緣356上，且封裝材料 276會包覆加勁構件350之頂面362及加勁構件35〇之底面 360。此外，加勁構件350的材質比如是鋼或是其他不易持 曲的材質。 〜 接著，請參照第11圖，在進行灌模製程之後，還要 進行如前所述之植上焊球及切割等步驟，最後會形成多個 獨立的晶片封裝體400，每^一晶片封裝體4〇〇均具有基板 10231twf.ptd 200411854 五、發明說明（9) 2 1 0、晶片2 3 0、多個導線2 8 0、加勁構件3 5 〇之頂 封裝材料276及焊球282，其構件之間的相關位置=6、 述，在此便不再贅述。 斤 綜上所述，本發明之具有散熱構件之多晶片 至少具有下列優點： 了衣核組 1·本發明之晶片封裝結構及其製程，由於加 具有較高之勁度’因此在進行切割製程時，尤其其/ 為甚薄的狀態下，比如約為〇.丨公釐到〇. 5公釐ς ,，係 加勁構件可以大幅縮減晶片封裝體之翹曲程度，二佶，= 板之下表面係呈現較為平整的狀態。故當晶片封裝體X 到一母板上時，基板邊緣位置相距母板之間的距離盥乂妬 中間位置相距母板之間的距離之間的差距會縮小，因 在基板邊緣位置的焊球在與母板接合後，即使經過 循環的操作下，亦可以避免產生破裂或剝離的現象。人… 2.本發明之晶片封裝結構及其製程， 基板與母板間接合的可靠度。 A 誕回 雖然本發明已以一較佳實施例揭露如上，麸盆 二限3發明，任何熟習此技藝者’在不脫離本發明之 精神和乾圍内，當可作久 赏/3之 保1 r円$、目a 各種更動與潤飾，因此本發明之 保邊犯圍虽視後附之申請專利範圍所界定者為準。 200411854 ......... _ 圖式簡單說明 苐1A圖綠示 〜'------ 視示意圖。 & 迷你球袼陣列封姑 ^ Ί D 衷在切割之前的上 第1B圖給示 面示意圖。、9 y、驾知逑你球格陣列封| / + # ^ 了衣在切割之後的剖 第2圖至第8 種迷你球格陣歹“二不依之照=發明第-較佳實施例之— 第3Α圖繪示/=剖面放大示意圖。 第9圖繪示 圖中加勁構件的上視示意圖。 球格陣列封裳制、^照本發明第一較佳實施例之另一種迷你 第1 0 - &之剖面放大示意圖。 —插、Φ於分圖^及第11圖緣示依照本發明第二較佳實施例之 ，^彳小球格陣列封裝製程之别面放大示意圖。 團式標示說明 晶片結構體 基板 晶片 封裝材料 導線 焊球 基板 上表面 晶片座 接點 下表面 接點 1023lw.ptd 第16頁 200411854 圖式簡單說明 230 晶 片 232 主 動 表 面 234 接 點 242 背 面 244 黏 著 材 料 250 加 勁 構 件 252 頂 部 254 側 壁 部 份 254a :上側 254b :下側 256 凸 緣 258 容 納 孔 260 開 V 262 頂 面 264 底 面 270 模 具 272 模 穴 274 頂 壓 部 276 封 裝 材 料 280 導 線 282 焊 球 290 黏 著 材 料 300 晶 片 封 裝 350 加 勁 構 件10231twf.ptd Page 13 200411854 V. Description of the invention (8) The application of the invention is not limited to this, adding f ^ 1 η. The strength ,, and σ structure can also be the shape without opening 1 ^ {^ f Μ1 It shows an enlarged schematic view of the brake surface of the second preferred two mini ball grid array sealing process according to the present invention. For the symbol of the needle application and the first-best implementation, ^: # λ 把 例The components specified in the description are the same as those in the first preferred implementation, and will not be repeated here. 'First tea photo No. 10', where the stiffening member 350 is a lid-like knot #, /, is constituted by a top 352, a side wall portion 354, and a flange 356, phase difference σ 卩 damage 3 5 4 The upper side 3 5 4 a is connected around the periphery of the top 3 5 2, and the side wall portion 354 is inclined to the top 352. A receiving hole 358 is formed by the top portion 352 and the side wall portion 354 of the stiffening member 350. It can accommodate multiple wafers 230, and the top 352 of the stiffening member 350 also has a top surface 362 and a corresponding bottom surface 36o. The bottom surface 36o of the stiffening member 350 faces the wafer 230 and the substrate 210. The flange 356 is connected around the lower side 354b of the side wall portion 354, and the flange 356 extends toward the outer direction of the receiving hole 358, and the extending direction is parallel to the top 3 5 2 and the stiffening member 3 5 0 The flange 356 is joined to the substrate 210, and when the mold is filled, the pressing portion 274 of the mold is pressed against the flange 356 of the stiffening member 350, and the packaging material 276 covers the stiffening member 350. The top surface 362 and the bottom surface 360 of the stiffener 35. In addition, the material of the stiffening member 350 is, for example, steel or other materials that are not easily bent. ~ Next, please refer to Figure 11, after the filling molding process, the steps of implanting solder balls and cutting as described above are also performed. Finally, a plurality of independent chip packages 400 will be formed, each chip package The body 400 has a substrate 10231twf.ptd 200411854 V. Description of the invention (9) 2 1 0, wafer 2 3 0, multiple wires 2 8 0, stiffening member 3 5 0, a top packaging material 276 and solder balls 282, which The relevant position between the components = 6, is not described here. As mentioned above, the multi-chips with heat-dissipating components of the present invention have at least the following advantages: The core assembly 1 · The chip packaging structure of the present invention and its manufacturing process, because it has a higher stiffness, so the cutting process is being performed. In particular, when it is in a thin state, for example, about 0.1 mm to 0.5 mm, stiffening components can greatly reduce the degree of warpage of the chip package. Second, = below the board The surface system is relatively flat. Therefore, when the chip package X is on a mother board, the distance between the edge position of the substrate and the mother board will be reduced, because the distance between the middle position and the mother board will be reduced. After joining with the motherboard, it can avoid cracking or peeling even after cyclic operation. People ... 2. The chip packaging structure and its process of the present invention, the reliability of the bonding between the substrate and the motherboard. A birthday. Although the present invention has been disclosed as above with a preferred embodiment, the bran basin is limited to 3 inventions. Anyone skilled in this art will not be departed from the spirit and scope of the present invention. 1 r 円 $, head a various changes and retouching, so the protection of the guilty infringement of the present invention is subject to the definition of the scope of the attached patent application. 200411854 ......... _ Brief description of the diagram 苐 1A green diagram ~ '------ View diagram. & Mini Ball 袼 Array Seal ^ Ί D Figure 1B shows the schematic diagram before cutting. , 9 y, driving know your ball grid array seal | / + # ^ Cut the clothing after cutting Figure 2 to 8 kinds of mini ball grid array 歹 "two different pictures = invention of the-the preferred embodiment of the — FIG. 3A shows a schematic enlarged cross-section. FIG. 9 shows a schematic top view of a stiffening member in the figure. The ball grid array seals are made according to another mini 10th embodiment of the first preferred embodiment of the present invention. -An enlarged schematic cross-sectional view of the &.-Insertion, Φ in the sub-map ^ and the edge of Fig. 11 are enlarged schematic diagrams of the other aspects of the small ball grid array packaging process according to the second preferred embodiment of the present invention. Description Wafer Structure Substrate Wafer Packaging Material Wire Solder Ball Substrate Upper Surface Wafer Contacts Lower Surface Contacts 1023lw.ptd Page 16 200411854 Schematic Brief Description 230 Wafer 232 Active Surface 234 Contact 242 Back 244 Adhesive Material 250 Stiffener 252 Top portion 254 Side wall portion 254a: Upper side 254b: Lower side 256 Flange 258 Receiving hole 260 Open V 262 Top surface 264 Bottom surface 270 Mold 272 Cavity 274 Pressing portion 276 Seal Material 280 conductor 282 with solder balls 290 sticky material package wafer 300 stiffener member 350

10231twf.ptd 第17頁 20041185410231twf.ptd Page 17 200411854

10231twf.ptd 第18頁10231twf.ptd Page 18

Claims (1)

200411854 六、申請專利範圍 1 · 一種晶片封裝製程，至少勺 提供一矩陣型基板； i · 配設複數個晶片於該矩 矩陣型基板電性連接； 暴板上，且該晶片與該 配設一加勁構件於該矩陣 _ 有一頂面及對應之—底面，基板上’s亥加勁構件具 矩陣型基板； - α勁構件之該底面係朝向該 β 一封裝材料以包覆該等晶片、錢陣型其板、 该加勁構件之該了蓋i 丁 土 I板、 苒千X頂面及該加勁構件之該底面； 切割該封裝材料、該铝p鱼剂I & η ^ 形成禝數個晶片封裴體。 霉件以 2·如申請專利範圍第丨項所述之晶片封裝 该加勁構件具有複數個開口，其位置對應於該歧 配 在該基板上的位置。 一日日月配置 3·如申請專利範圍第丨項所述之晶片封裝製程，豆 該加勁構件之該底面係朝向該些晶片。 I/、 4·如申請專利範圍第1項所述之晶片封裝製程，其中 該散熱構件係藉由一黏著材料與該基板接合。 〃 5·如申請專利範圍第1項所述之晶片封裝製程，其中 在切別該晶片、該基板及該加勁構件之後，還形成複數個 焊球於該基板上。200411854 6. Scope of patent application 1. A wafer packaging process, at least a matrix substrate is provided; i. A plurality of wafers are electrically connected to the rectangular matrix substrate; a storm board is provided, and the wafer is provided with one The stiffening member has a top surface and a corresponding-bottom surface, and the substrate of the stiffening member has a matrix-type substrate;-the bottom surface of the α stiffening member is oriented toward the β a packaging material to cover the chips, money arrays, etc. Plate, the stiffening member, the cover, the I plate, the top surface of the stiffening member, and the bottom surface of the stiffening member; cutting the packaging material, the aluminum pectin I & η ^ to form several wafer seals body. The mold is packaged in the wafer as described in item 1 of the patent application scope. The stiffening member has a plurality of openings, and its position corresponds to the position of the discrepancy on the substrate. Day, month, and month configuration 3. According to the wafer packaging process described in item 丨 of the patent application scope, the bottom surface of the stiffening member faces the wafers. I /, 4. The chip packaging process according to item 1 of the scope of patent application, wherein the heat dissipation member is bonded to the substrate by an adhesive material. · 5. The wafer packaging process according to item 1 of the scope of patent application, wherein after cutting the wafer, the substrate and the stiffening member, a plurality of solder balls are formed on the substrate. 6·如申請專利範圍第1項所述之晶片封裝製程，其中 在切割該晶片、該基板及該加勁構件之前，還形成複數個 焊球於該基板上。 10231 twf.ptd 第19貢 2004118546. The wafer packaging process according to item 1 of the scope of patent application, wherein a plurality of solder balls are formed on the substrate before the wafer, the substrate and the stiffening member are cut. 10231 twf.ptd The 19th tribute 200411854 六、申請專利範圍 7·如申請專利| 在配設該晶片於該基 附於該基板上，且還 性連接該晶片與該基 L圍第1項所述之晶 板上時，該晶片係 進行一打線製程以 板0 片封裝製程，其中 藉由一黏著材料貼 形成複數條導線電 8.如申請專利範圍第1項所述之晶片封 該加勁構件的材質係為銅。 、I %，其中 9 · 一種晶片封裝體’至少包括· 一基板； . aa 片 配置在該基板上 連接； 且該晶片與該基板電性 一加勁構件，配置在該基板上，該加勁構件且 頂面及對應之一底面，該加勁構件 亥 /、 板；以及 力偁仟之3底面係朝向該基 該基板、該加勁構件之 一封裝材料，包覆該晶片 該頂面及該加勁構件之該底面£ 1 〇 ·如申請專利範圍第9項所述之晶片封裝體，其中 該加勁構件具有一開口，其位置對應於該晶片在該 板上的位置。 直你 11 ·如申請專利範圍第9項所述之晶片封裝體，其中 該加勁構件之該底面係朝向該晶片。 1 2 ·如申叫專利枕圍第9項所述之晶片封裝體，還包 括複數個導線，而該晶片係貼附於該基板上，藉由該些導 線與該基板電性連接。 1 3 ·如申請專利範圍第9項所述之晶片封裝體，其中6. Scope of Patent Application 7 · If applying for a patent | When the wafer is arranged on the substrate and attached to the substrate, and the wafer is also connected to the crystal plate described in item 1 of the substrate, the wafer is A wire bonding process is carried out with a 0-chip packaging process, in which a plurality of wires are formed by an adhesive material. 8. The chip encapsulation of the stiffening member as described in item 1 of the patent application scope is made of copper. 1%, of which 9 a chip package includes at least a substrate; aa chip is configured to be connected on the substrate; and the chip is electrically connected to the substrate with a stiffening member disposed on the substrate, the stiffening member and The top surface and the corresponding one of the bottom surface, the stiffening member, the plate; and the bottom surface of the force 3 are facing the base substrate, one of the encapsulating material of the stiffening member, and covering the top surface of the wafer and the stiffening member. The bottom surface is £ 10. The chip package according to item 9 of the patent application scope, wherein the stiffening member has an opening corresponding to the position of the wafer on the board. Straight You 11 · The chip package as described in item 9 of the patent application scope, wherein the bottom surface of the stiffening member faces the chip. 1 2 · The chip package according to item 9 of the patent claim, which also includes a plurality of wires, and the chip is attached to the substrate, and is electrically connected to the substrate through the wires. 1 3 · The chip package as described in item 9 of the patent application scope, wherein 10231twf.ptd 第20頁 200411854 六、申請專利範圍 該加勁構件的材質係為銅。 14·_一種晶片封裝體，至少包括·· 一溥型基板，該薄型基板的 1公釐之間； 子及係，丨於U· 5公釐到〇· 日日片，配置在該薄型基板上，且該晶片斑# ^ 基板電性連接； a日日Λ興忒溽型 二加，構件，配置在該薄型基板上；以及 件。—封裝材料，包覆該晶片、該薄型基板及該加勁構 二J1 5.如申請專利範圍第1 4項所述之晶片封裝體，1由 忒加勁構件具有—頂面及對應之一底面，該加勁構件^ 底面係朝向該薄型基板，而該封裝材料係包覆該加勁構^ 之該頂面及該加勁構件之該底面。 一1 6 ·如申請專利範圍第1 5項所述之晶片封裝體，其中 該加勁構件之該底面係朝向該晶片。 八 ^ 7.如申請專利範圍第1 4項所述之晶片封裝體，其中 該加勁構件具有一開口，其位置對應於該晶片配置在該薄 型基板上的位置。 1 8 ·如申睛專利範圍第1 4項所述之晶片封裝體，還包 括複數個導線，而該晶片係貼附於該薄型基板上，藉由該 些導線與該薄型基板電性連接。 1 9·如申請專利範圍第丨4項所述之晶片封裝體，其中 該加勁構件的材質係為鋼。 凸 2 0 · —種加勁構件，包括/谓部、一侧壁部份及10231twf.ptd Page 20 200411854 VI. Scope of patent application The material of the stiffener is copper. 14 · _A chip package including at least a 溥 -shaped substrate, between 1 mm of the thin substrate; a sub-system, and a U-chip of 5 mm to 0 · day, arranged on the thin substrate And the wafer spot is electrically connected to the substrate; a day-to-day Xingye type two plus, a component, is disposed on the thin substrate; and a piece. —Packaging material, covering the chip, the thin substrate and the stiffening structure J1 5. The chip package as described in item 14 of the scope of patent application, 1 is made of a stiffening member—a top surface and a corresponding bottom surface, The bottom surface of the stiffening member ^ faces the thin substrate, and the packaging material covers the top surface of the stiffening member ^ and the bottom surface of the stiffening member. -16-The chip package as described in item 15 of the scope of patent application, wherein the bottom surface of the stiffening member faces the wafer. ^ 7. The chip package according to item 14 of the scope of patent application, wherein the stiffening member has an opening corresponding to a position where the chip is disposed on the thin substrate. 18 · The chip package as described in item 14 of the Shenjing patent scope further includes a plurality of wires, and the chip is attached to the thin substrate and is electrically connected to the thin substrate through the wires. 19 · The chip package as described in item 4 of the patent application scope, wherein the material of the stiffening member is steel. Convex 2 0 · — a kind of stiffening member, including / predicate part, a side wall part and 200411854 六 申睛專利範圍 ___ —__ 緣，該側壁部份一 ^ -側係連接該凸緣，二1係連接於該頂㉝，該側壁部份之另 係傾斜於該側 〜則壁部份係傾斜於該頂部，該凸緣 配置在該加勁構件二並且該加勁構件還具有至少-開口 21 功偁件之該頂部上。 數個開口如Ιϊ專利範圍第20項所述之加勁構件，具有複 頂部。 /、係以矩陣排列的方式配置在該加勁構件之該 2 2 ·如申請專利範圍第2 0項所述之加勁構件，立中嗜 凸緣的延伸方向係平行於該頂部。 '、° .23.如申請專利範圍第2〇項所述之加勁構件，其材質 係為銅。 、200411854 Six patent application scope ___ —__ Edge, one side of the side wall is connected to the flange, two side is connected to the top, the other side of the side wall is inclined to the side ~ the wall part The component is inclined to the top, and the flange is disposed on the top of the stiffening member 2 and the stiffening member also has at least an opening 21 function member. Several openings are stiffening members as described in item 20 of the patent scope and have a multiple top. /. The stiffeners are arranged in a matrix arrangement in the matrix. 2 · As for the stiffeners described in item 20 of the scope of the patent application, the extension direction of the neutral center flange is parallel to the top. ', ° .23. The stiffening member described in item 20 of the scope of patent application, the material of which is copper. , 第22貢22nd Tribute
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