[go: up one dir, main page]

TW200408319A - Warpage-preventing circuit board and method for fabricating the same - Google Patents

Warpage-preventing circuit board and method for fabricating the same Download PDF

Info

Publication number
TW200408319A
TW200408319A TW091132545A TW91132545A TW200408319A TW 200408319 A TW200408319 A TW 200408319A TW 091132545 A TW091132545 A TW 091132545A TW 91132545 A TW91132545 A TW 91132545A TW 200408319 A TW200408319 A TW 200408319A
Authority
TW
Taiwan
Prior art keywords
circuit board
conductive
thermal deformation
substrate
scope
Prior art date
Application number
TW091132545A
Other languages
English (en)
Other versions
TWI229574B (en
Inventor
Chin-Huang Chang
Han-Ping Pu
Chung-Lun Liu
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW091132545A priority Critical patent/TWI229574B/zh
Priority to US10/441,647 priority patent/US6864434B2/en
Publication of TW200408319A publication Critical patent/TW200408319A/zh
Priority to US11/043,496 priority patent/US7266888B2/en
Application granted granted Critical
Publication of TWI229574B publication Critical patent/TWI229574B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09663—Divided layout, i.e. conductors divided in two or more parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base
    • Y10T29/4916—Simultaneous circuit manufacturing

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Structure Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

五、·發'明說明（1) [發明領域] 本發明係有關你 , -種可防止熱變形之；J半導體封裝技術，特別是有關於 [發明背景] 之電路板及其製法。 半導體晶片封奘+ 祚為θ Η哉目 了衣技術—般係採用基板（substrate)來 二曰曰乃戰八’用以安置於一半導 半導體晶片可透過其紅工一 A夕似]干夺版曰曰片，以讓 ^ ^ , ± 、基板而耦接至外部的印刷電路板。舉例 用一 AP列式（Bal 1 Grid Array，BGA)封裴技術即採 L冊：=置半導體晶片，並於基板背面植置上複數個 4”:排列之銲球’以藉由此些銲球將整個的晶片封 衣早=干力及電性連接至外部之印刷電路板。 一第1 A圖即顯示一種習知之BGA基板i 〇 〇的頂視圖。如圖 戶f示此基板1⑽之表面上係預先定義出至少一置晶區（如 心號1 1 0所‘之虛線框所包含之部分），且該置晶區11 〇中 设置有複數條導電跡線（traces)120。使得該基板100表面 上位於该些導電跡線i 2 0以外之區域為一空白區域i 3 〇而未 設置有任何電路元件。接著於該基板1 〇 〇上另形成有一拒 銲層（solder mask)140，其係覆蓋住該基板1〇〇的導電跡 線1 2 0和空白區域1 3 0，用以作為後續之迴銲程序（s 〇丨d e r @ f 1 ow)時的罩幕。 跡線 ，致使該不同疏密之導電跡線1 2 0產生大小不同的熱應力， 因而造成該基板1 〇 〇的翹曲，進而影響置晶作業之進行， 然而如第1 B圖所示’上述基板1 〇 〇之缺點在於其導電 1 2 0之分佈疏密不均，容易在封裝製程中因溫度效應
I6953.ptd 第8頁 200408319 五、發明說明（2) 甚至導致接置於該基板1 0 0上之半導體晶片15 0破相並造成 電子產品之品質缺陷等重大問題。 美國專利第 6, 380, 633號"PATTERN LAYOUT STRUCTURE IN SUBSTRATE11即針對上述之問題而提出了一種解決方 法，亦即於基板上未佈設有導電跡線之空白區域上設置有 連續型之假導電線路塊（dummy circuit region)0 第2 A圖即顯示一採用上述之專利技術的基板2 0 0的頂 視結構形態。如圖所示，該基板2 0 0之表面預定有至少一 置晶區2 1 0，且該置晶區2 1 0中設置有複數條導電跡線 2 2 0。此外，該基板2 0 0之表面上位於該些導電跡線2 2 0以 外之表面區域設置有一連續型之假導電線路塊2 3 0。該連 續性之假導電線路塊2 3 0係均勻的分佈於基板2 0 0表面，使 該分佈疏密不均之導電跡線2 2 0得以容置於該分佈均勻之 假導電線路塊2 3 0中，進而減少該導電跡線2 2 0因疏密佈置 所造成之基板翹曲問題。 然而上述之基板2 0 0的一項缺點在於該假導電線路塊 2 3 0的材質為銅（Cu)，其熱膨脹係數（c〇ef f icient 〇f Thermal Expansion，CTE#16ppm/cc，而該基板 2〇〇之材 質一般為B T ’其熱膨脹係數為1 4 p p m /艺，因此在不當佈置 密度的假導電線路塊2 3 0於封裝製程之高溫處理過程中， 例如為烘烤程序、迴銲程序、和模鑄程序時，仍將由於假 導電線路塊2 3 0和基板2 0 0之間的熱膨脹係數差異，而致使 該基板2 0 0因熱變形產生翹曲（Warpage)現象。
*五：#明說明（3) 的薄片型 TFBGA(Thin Fine〜piUh • ’其可此使得基板表面的輕曲 重影響到置晶作業之進行。 王 [發明概述] 鑒於以上所述習知技術之缺點 於提供一種可防止熱變形之電路 路板於封裝製程中產生熱變形現= 而導致晶片之破裂，使得完成封壯 品質性及信賴性。 & •為達成上揭及其他目的，本發 形之電路板及其製法。該電路板係 材；複數條導電跡線（Conduetive' 絕緣性基材之表面；複數個區塊化 塊，係設置於該導電跡線外之表面 鄰之假導電線路塊之間設置有一伸 質層’敷設至該電絕緣性基材表面 線及該區塊化之不連續性假導電線 本發明提供了一種可防止熱變 其特點在於至少一電路板表面上佈 _域，設置有複數個區塊化之不連 於各對相鄰之假導電線路塊之間形 導體製程南〉孤處理過程中，利用該 分散熱應力，並透過該伸縮縫以緩 熱膨脹，而防止電路板產生熱變形 D Grid Array)基板 &達到50mm-70mm而嚴 ’本發明之主要目的在 及其製法，用以防止電 @造成置晶作業困難甚 之半導體裝置具更佳之 明揭露一 包括 ：— Trace)， 之不連續 區域’並 縮縫；以 上，以遮 路塊。 形之電路 設有多數 續性假導 成一伸縮 不連續性 衝該些假 而造成接 止熱變 性基 於該電 種可防 電絕緣 係設置 性假導電線路 於該每一對相 及一絕緣性材 覆住該導電跡 板及其 導電跡 電線路 縫，藉 之導電 導電線 置其上 製法， 線外之 塊，並 以在半 線路塊 路塊之 之晶片
16953.Ptd 苐10頁 200408319 五、發明說明（4) 產生破裂之現象，使得置晶作業得以順利進行，同時提供 封裝完成之半導體裝置具更佳之品質性及信賴性。 [發明實施例] 以下即配合所附之圖式中的第3圖至第5圖，詳細揭露 說明本發明之可防止熱變形之電路板及其製法之實施例。 此處須注意的一點是，第3圖至第5圖均為簡化之示意圖 式，其僅係以示意方式說明本發明之基本構想；因此其僅 顯示與本發明有關之元件，且所顯示之元件並非以實際實 施時之數目、形狀、及尺寸比例纷製；其實際實施時之數 目、形狀、及尺寸比例可為一種隨意性之設計選擇，且其 元件佈局形態可能更為複雜。 請首先參閱第3及第4圖’其中顯示本發明之可防止熱 變形之電路板3 0 0示意形態。如圖所示，該電路板3 0 0係包 括：一電絕緣性基材3 0 1 ;複數條導電跡線3 2 0，係設置於 該電絕緣性基材3 0 1至少一表面；複數個區塊化之不連續 性假導電線路塊3 3 0，係設置於該導電跡線3 2 0外之表面區 域，並於該每一對相鄰之假導電線路塊3 3 〇之間設置有一 鋸齒狀之伸縮縫3 3 1 ;以及一絕緣性材質層3 4 0，敷設至該 電絕緣性基材3 0 1表面上，以遮覆住該導電跡線3 2 0及該區 塊化之不連續性假導電線路塊3 3 0。 該電路板3 0 0為一球柵陣列式（BGA)基板，該電絕緣性 基材301可為一芯層Layer)，該怒層得以樹脂材質 如環氧樹脂（Ε ρ ο X y r e s i n)、聚亞醯胺（P 〇 1 y i m i d e )樹脂、 BT(Bismaleimide Trazine)樹脂、FR4樹脂等製成。然
第11 X 200408319 •五^明說明（5) 後，於芯層之相對第一表面3 0 1 a及第二表面3 0 1 b上各壓合 至少一銅（Copper)層，使銅層經曝光（Exposing)、顯影 (Developing)、蝕刻（Etching)等製程而圖案化 (Patterning)以形成多數導電跡線3 2 0a及3 2 0 b。此外，於 該芯層之第一表面3 0 1 a係形成有一置晶區，用以承载晶片 (未圖示），而第二表面301 b則得植接多數導電元件如銲球 —(未圖示）以與外界電性連接。 該區塊化之不連續性假導電線路塊3 3 0，係設置於該 芯層之第一及第二表面3 0 1 a、3 0 1 b上未佈設有導電跡線 • 0 a、3 0 2 b之表面區域，並於該每一對相鄰之假導電線路 塊3 3 0之間設置有一伸縮縫3 3 1。該區塊化之不連續性假導 電線路塊3 3 0的面積尺寸係設計成小於一預先由實驗結果 定出之熱變形臨界面積尺寸；亦即若一塊個別之假導電線 路塊3 3 0大於此臨界面積尺寸則會使得基板產生會影響到 置晶程序的熱變形現象，而小於此臨界面積尺寸則不致使 得基板產生會影響到置晶程序的熱變形現象。請參閱第5 圖，即顯示上述之伸縮縫3 3 1呈梯形鋸齒的另一種實施方 式，其中係將伸縮縫3 3 1以一鋸齒狀延伸於相鄰之二個假 導電線路塊3 3 0之間，即可利用該不連續性之導電線路塊 •β 〇分散製程中所產生之熱應力，並透過該伸縮縫3 3 1以緩 衝該些假導電線路塊3 3 0之熱膨脹。 該絕緣性材質層3 4 0如拒銲層（s〇ider Mask)340a、 -3 4 0 b係分別敷設至芯層3 0 1之第一表面3 〇 1 a及第二表面 3 0 1 b上，以遮覆住第一及第二導電跡線3 2 0 a、3 2 0 b與該假
16953.pid
200408319 五、發明說明（6) 導電線路塊3 3 0，而令第一導電跡線3 2 0 a之薛指3 5 0及第 二導電跡線3 2 0 b之銲墊3 7 0外露出該拒銲層3 4 0 a、3 4 0 b 。藉由該拒銲層340a、340b包覆之導電跡線320a、320b 及假導電線路塊3 3 0得避免外界水氣或污染物對其之侵 害，並得防止後續製程中因導電跡線外露而產生短路 (Short Circuit)、影響電性品質等問題。 而於製備该球拇陣列式基板時，首先，於芯層之相對 弟 表面3 0 1 a及弟^一表面3 0 1 b上各壓合至少^—銅（Copper) 層’使銅層經曝光（Exposing)、顯影（Developing)、蝕刻 (Etching)專製程而圖案化（pauerning)以形成多數導電 跡線3 2 0 ;以及在未佈設有導電跡線3 2 0之表面區域上，形 成有多數區塊化之不連續性假導電線路塊3 3 〇，並於該每 一對相鄰之假導電線路塊3 3 〇之間設置有一鋸齒狀之伸縮 縫3 3卜 之後’分別敷設拒銲層（S 〇 1 d e r M a s k) 3 4 0 a、3 4 0 b係 至芯層3 0 1之第一表面3 〇丨a及第二表面3 〇丨b上，以遮覆住 第一及第二導電跡線3 2 0 a、3 2 0 b與該假導電線路塊3 3 0， 而令第一導電跡線3 2 0 a之銲指3 5 0及第二導電跡線3 2 0 b 之銲塾3 7 0外露出該拒銲層34〇a、34〇b，以完成該可防止 熱變形之基板 。 請爹閱第6圖，係應用該可防止熱變形之基板於球柵 陣列式（B G A )半導體封裝件之製程中。該基板4 〇 〇具有一置 晶面4 0 0 a及一相對之植球面4 〇 〇 b，該置晶面4 0 0 a係對應於 該基板4 0 0中芯層4 0 1之第一表面4 0 1 a，而植球面4 0 0 b係對
:69?3.ptd 13頁 200408319 1五：4明說明⑺ 應於芯層之第二表面4 0 1 b。 接著進行一置晶程序，藉此將至少一半導體晶片4 8 0 藕接至該基板4 0 0的置晶面4 0 0 a上。並進行一銲線（W i re Bonding)作業以形成多數銲線481如金線（Gold Wire)，該 銲線4 8 1銲接至外露出絕緣性材質層4 4 0之第〆導電跡線 4 2 0 a的銲指4 5 0以及晶片4 8 0，藉以電性連接該晶片4 8 0至 基板4 0 0之置晶面4 0 0 a。 進行一模壓（Μ ο 1 d i n g )作業，以使用一樹脂化合物如 環氧樹脂等於基板4 0 0之置晶面4 0 0 a上形成一封裝膠體 擊neapsul ant ) 4 9 0，藉之以包覆該半導體晶片48 0及銲線 4 8 1，使其與外界氣密隔離而免受外界水氣、污染物之侵 害。 完成模壓作業後，進行一模壓後固化（Post Molding
Curing，PMC)製程，使形成於基板4 0 0之置晶面4 0 0a上的 封裝膠體4 9 0歷經約1 7 5: C之溫度、歷時約6小時之烘烤而 固化（Curing)。 最後’進行一植球（B a 1 1 I m p 1 a n t a t i ο η )作業以植接 夕數杯球4 9 1於基板4 〇 〇之植球面4⑽b上外露出絕緣性材質 層4 4 0之第二導電跡線4 2 0 b的銲墊4 7 0，以使銲球4 9 1作為、 春導體封裝件之輸入/輸出（Inpu1：/〇utput，1/〇)端而令晶 片48 0得與外界裝置如印刷電路板（未圖示）成電性連接7關曰曰 於上述之高溫製程過程中，例如為烘烤程序、迴銲裎 序、和模鑄程序時，其高溫環境將使得該假導電線路^壬
200408319 五、發明說明（8) 4 3 0產生熱膨脹現象；但由於該假導電線路塊4 3 0的面積尺 寸係小於熱變形臨界面積尺寸，因此其個別的熱膨脹現象 不致使得基板4 0 0產生會影響到置晶程序的熱變形現象； 且由於該假導電線路塊4 3 0之間的伸縮縫4 3 1的緩衝作用， 因此可緩衝該些假導電線路塊4 3 0的熱膨脹現象而不會因 擠壓到鄰旁之假導電線路塊4 3 0而產生熱變形現象。 惟以上所述者僅為本發明之較佳實施例而已，並非用
以限定本發明之實質技術内容的範圍。本發明之實質技V 内容係廣義地定義於下述之申請專利範圍中。若住二術 、 I Μ他人 所完成之技術實體或方法與下述之申請專利範圍所定 為完全相同、或是為一種等效之變更，均將被視為q #者 此專利範圍之中。章節結束 盖於
200408319 1圖盖簡>單說明 [圖式簡述] 第I A圖為一習知基板之跡線佈設頂視圖； 第I B圖為一構建於第I A圖所示之基板發生麵曲’造成 接置其上之晶片產生破損之剖面示意圖； 第2圖為一習知之具有假導電線路塊的基板的頂視 圖， 第3圖為本發明中具有假導電線路塊之可防止熱變形 之電路板頂視圖； 第4圖為本發明中具有假導電線路塊之可防止熱變形 φ電路板剖面示意圖； 第5圖為本發明中可防止熱變形之電路板的假導電線 路塊之間的伸縮縫結構形態示意圖；以及 第6圖為本發明可防止熱變形之電路板於BGA半導體封 裝件之結構形態示意圖。 [圖i 式標 號 說 明] 100 基 板 110 置 晶 區 120 導 電 跡 線 130 空 白 區 域 140 拒 銲 層 150 晶 片 151 晶 片 1 5 0上的破裂現象 200 基 板 «° 置 晶 220 導 電 跡 線 230 連 續 型 之假導電線路塊 240 拒 鮮 層 2 5 0 晶片 -3 0 0 可防止熱變形之電路板 3 0 I 電絕緣性基材 3 2 0 複數條導電跡線
I6953.ptd 第16 200408319
第17頁 圖式簡單說明 330 假 導 電 線 路 塊 331 伸 縮 縫 340 絕 緣 性 材 質 層 301a 第 一 表 面 301b 第 二 表 面 3 2 0a 導 電 跡 線 3 2 0b 導 電 跡 線 340a 拒 銲· 層 34 0b 拒 銲 層 350 録 指 370 銲 墊 400 基 板 4 0 0a 置 晶 面 4 0 0b 植 球 面 401 層 401a 第 一 表 面 401b 第 二 表 面 4 2 0a 第 一 導 電 跡 線 42 0b 第 二 導 電 跡 線 430 假 導 電 線 路 塊 431 伸 縮 縫 440 絕 緣 性 材 質 層 450 銲 指 470 銲 墊 480 晶 片 481 銲 線 490 封 裝 膠 體 491 銲 球

Claims (1)

  1. 200408319 ^ (中、膏專利範圍 1. 一種可防止熱變形之電路板，包括： 一電絕緣性基材； 複數條導電跡線，係設置於該電絕緣性基材之至 少一表面上； 複數個區塊化之不連續性假導電線路塊（d u m m y c i r c u i t r e g i ο η )，係設置於該電絕緣性基材之表面上 位於該些導電跡線外之表面區域，且該每一對相鄰之 假導電線路塊之間設置有一伸縮缝；以及 一絕緣性材質層，係形成於該電絕緣性基材表面 ’用以覆盖住該些導電跡線和假導電線路塊。 2. 如申請專利範圍第1項之可防止熱變形之電路板，其中 ，該假導電線路塊為銅製。 3. 如申請專利範圍第1項之可防止熱變形之電路板，其中 ，該假導電線路塊之間的伸縮縫係以一鋸齒狀延伸於 該些假導電線路塊之間。 4. 如申請專利範圍第1項之可防止熱變形之電路板，其中 ，該電路板為一 B G A基板。 5. 如申請專利範圍第1項之可防止熱變形之電路板，其中 ，該電絕緣性基材為一芯層（C 〇 r e )。 _如申請專利範圍第1項之可防止熱變形之電路板，其中 ，該絕緣性材質層為一拒銲層（S ο 1 d e r M a s k )。 7 . —種可防止熱變形之電路板製法，係包括： 於一電絕緣性基材之至少一表面形成有多數之導 電跡線；
    16953.ptd 第18頁 200408319 六、申請專利範圍 於該佈設有導電跡線外之表面區域形成有複數個 區塊化之不連續性假導電線路塊，並於該每一對相鄰 之假導電線路塊之間設置有^一缝隙，以及 形成一絕緣性材質層於該電絕緣性基材表面，用 以覆蓋住該些導電跡線和假導電線路塊。 8. 如申請專利範圍第7項之可防止熱變形之電路板製法， 其中，該電路板為一 B G A基板。 9. 如申請專利範圍第7項之可防止熱變形之電路板製法， 其中，該電絕緣性基材為一芯層。 1 0 .如申請專利範圍第7項之可防止熱變形之電路板製法， 其中，該假導電線路塊為銅製。 1 1.如申請專利範圍第7項之可防止熱變形之電路板製法， 其中，該假導電線路塊之間的伸縮缝係以一鋸齒狀延 伸於該些假導電線路塊之間。 1 2 .如申請專利範圍第7項之可防止熱變形之電路板製法， 其中，該絕緣性材質層為一拒銲層（S ο 1 d e r M a s k)。
TW091132545A 2002-11-05 2002-11-05 Warpage-preventing circuit board and method for fabricating the same TWI229574B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW091132545A TWI229574B (en) 2002-11-05 2002-11-05 Warpage-preventing circuit board and method for fabricating the same
US10/441,647 US6864434B2 (en) 2002-11-05 2003-05-19 Warpage-preventive circuit board and method for fabricating the same
US11/043,496 US7266888B2 (en) 2002-11-05 2005-01-25 Method for fabricating a warpage-preventive circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW091132545A TWI229574B (en) 2002-11-05 2002-11-05 Warpage-preventing circuit board and method for fabricating the same

Publications (2)

Publication Number Publication Date
TW200408319A true TW200408319A (en) 2004-05-16
TWI229574B TWI229574B (en) 2005-03-11

Family

ID=32173893

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091132545A TWI229574B (en) 2002-11-05 2002-11-05 Warpage-preventing circuit board and method for fabricating the same

Country Status (2)

Country Link
US (2) US6864434B2 (zh)
TW (1) TWI229574B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111526678A (zh) * 2020-04-28 2020-08-11 维沃移动通信(重庆)有限公司 电子设备的壳体及电子设备

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050077080A1 (en) * 2003-10-14 2005-04-14 Adesoji Dairo Ball grid array (BGA) package having corner or edge tab supports
TW591985B (en) * 2003-10-15 2004-06-11 Benq Corp PCB having a circuit layout for preventing the PCB from bending when heated
US7223923B2 (en) * 2004-10-26 2007-05-29 Hannstar Display Corporation PCB capable of releasing thermal stress
CN100392845C (zh) * 2004-11-12 2008-06-04 日月光半导体制造股份有限公司 在基板和封装胶体间具有高粘着性的封装结构
JP4768994B2 (ja) * 2005-02-07 2011-09-07 ルネサスエレクトロニクス株式会社 配線基板および半導体装置
US7838779B2 (en) * 2005-06-17 2010-11-23 Nec Corporation Wiring board, method for manufacturing same, and semiconductor package
DE602006012833D1 (de) * 2005-06-24 2010-04-22 Taiwan Semiconductor Mfg Substrate zur verhinderung von wellungen und herstellungsverfahren dafür
US20070001285A1 (en) * 2005-06-30 2007-01-04 Hem Takiar Apparatus having reduced warpage in an over-molded IC package
US7538438B2 (en) * 2005-06-30 2009-05-26 Sandisk Corporation Substrate warpage control and continuous electrical enhancement
US20070004094A1 (en) * 2005-06-30 2007-01-04 Hem Takiar Method of reducing warpage in an over-molded IC package
KR101015265B1 (ko) * 2005-06-30 2011-02-18 샌디스크 코포레이션 오버 몰딩된 ｉｃ 패키지의 휨을 줄이는 방법
TW200704323A (en) * 2005-07-01 2007-01-16 Lite On It Corp Printed circuit board
JP2007266048A (ja) * 2006-03-27 2007-10-11 Orion Denki Kk 位置合わせ方法及び基板
US20070269929A1 (en) * 2006-05-17 2007-11-22 Chih-Chin Liao Method of reducing stress on a semiconductor die with a distributed plating pattern
WO2007136651A2 (en) * 2006-05-17 2007-11-29 Sandisk Corporation Semiconductor device with a distributed plating pattern
US20070267759A1 (en) * 2006-05-17 2007-11-22 Chih-Chin Liao Semiconductor device with a distributed plating pattern
TWI308385B (en) * 2006-08-09 2009-04-01 Unimicron Technology Corp Package substrate
US7679002B2 (en) * 2006-08-22 2010-03-16 Texas Instruments Incorporated Semiconductive device having improved copper density for package-on-package applications
CN100583424C (zh) * 2006-09-20 2010-01-20 欣兴电子股份有限公司 封装基板
US8014154B2 (en) * 2006-09-27 2011-09-06 Samsung Electronics Co., Ltd. Circuit substrate for preventing warpage and package using the same
JP2009088173A (ja) * 2007-09-28 2009-04-23 Fujitsu Ltd 配線基板
TWI432121B (zh) * 2008-02-18 2014-03-21 Princo Corp 平衡多層基板應力之方法及多層基板結構
US20110212307A1 (en) * 2008-02-18 2011-09-01 Princo Corp. Method to decrease warpage of a multi-layer substrate and structure thereof
US20110212257A1 (en) * 2008-02-18 2011-09-01 Princo Corp. Method to decrease warpage of a multi-layer substrate and structure thereof
JP2010135418A (ja) 2008-12-02 2010-06-17 Shinko Electric Ind Co Ltd 配線基板及び電子部品装置
TWI384603B (zh) 2009-02-17 2013-02-01 Advanced Semiconductor Eng 基板結構及應用其之封裝結構
US20100270061A1 (en) * 2009-04-22 2010-10-28 Qualcomm Incorporated Floating Metal Elements in a Package Substrate
US8397380B2 (en) * 2009-06-01 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling warpage in BGA components in a re-flow process
KR101037450B1 (ko) * 2009-09-23 2011-05-26 삼성전기주식회사 패키지 기판
KR101179399B1 (ko) * 2010-10-04 2012-09-04 삼성전기주식회사 크로스토크를 저감하기 위한 인쇄회로기판
US20130153266A1 (en) * 2011-12-19 2013-06-20 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same
KR20130077537A (ko) * 2011-12-29 2013-07-09 삼성전기주식회사 회로기판
JP6039318B2 (ja) * 2012-08-31 2016-12-07 矢崎総業株式会社 プリント配線基板
US8823170B2 (en) * 2012-12-06 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for three dimensional integrated circuits
KR20150049084A (ko) * 2013-10-29 2015-05-08 삼성전기주식회사 인쇄회로기판
CN104701246B (zh) * 2013-12-10 2018-03-23 展讯通信（上海）有限公司 芯片及形成方法、封装成品、提高封装成品良率的方法
CN104701245B (zh) * 2013-12-10 2018-07-31 展讯通信（上海）有限公司 芯片形成方法、提高芯片封装成品良率的方法
US10070547B2 (en) * 2014-02-26 2018-09-04 Sparton Corporation Control of electric field effects in a printed circuit board assembly using embedded nickel-metal composite materials
US20150245548A1 (en) * 2014-02-26 2015-08-27 Sparton Corporation Control of electric field effects in a printed circuit board assembly using embedded nickel-metal composite materials
KR101540070B1 (ko) 2014-10-27 2015-07-29 삼성전자주식회사 패키지 기판 및 반도체 패키지의 제조방법
US9818682B2 (en) * 2014-12-03 2017-11-14 International Business Machines Corporation Laminate substrates having radial cut metallic planes
KR101733442B1 (ko) * 2014-12-29 2017-05-10 주식회사 케이씨씨 기판의 휨 방지 구조체
KR20170000458A (ko) * 2015-06-23 2017-01-03 삼성전자주식회사 기판 스트립
US9659884B2 (en) * 2015-08-14 2017-05-23 Powertech Technology Inc. Carrier substrate
WO2018004684A1 (en) 2016-07-01 2018-01-04 Intel Corporation Semiconductor packages with antennas
US10854556B2 (en) * 2016-10-12 2020-12-01 Advanced Semiconductor Engineering Korea, Inc. Semiconductor package device and method of manufacturing the same
WO2018150560A1 (ja) * 2017-02-20 2018-08-23 新電元工業株式会社 電子装置
KR102329799B1 (ko) 2017-08-11 2021-11-22 삼성전자주식회사 반도체 패키지
US20200250349A1 (en) * 2017-08-25 2020-08-06 Smartpak Technology Llc Security systems incorporating circuitry connectable to the internet of things
KR102437245B1 (ko) 2017-10-24 2022-08-30 삼성전자주식회사 인쇄회로기판 및 그를 포함하는 반도체 패키지
KR102127817B1 (ko) * 2018-07-13 2020-06-29 삼성전기주식회사 인쇄회로기판
US11432402B2 (en) * 2018-10-11 2022-08-30 Microchip Technology Caldicot Limited Flipped-conductor-patch lamination for ultra fine-line substrate creation
US11452199B2 (en) * 2019-09-12 2022-09-20 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic module with single or multiple components partially surrounded by a thermal decoupling gap

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134246A (en) * 1990-05-07 1992-07-28 Kyocera America, Inc. Ceramic-glass integrated circuit package with integral ground and power planes
JP3066251B2 (ja) * 1994-08-05 2000-07-17 シャープ株式会社 プリント配線基板
JP4045648B2 (ja) * 1998-06-10 2008-02-13 ソニー株式会社 半導体装置
US6204559B1 (en) * 1999-11-22 2001-03-20 Advanced Semiconductor Engineering, Inc. Ball grid assembly type semiconductor package having improved chip edge support to prevent chip cracking
US6534852B1 (en) * 2000-04-11 2003-03-18 Advanced Semiconductor Engineering, Inc. Ball grid array semiconductor package with improved strength and electric performance and method for making the same
JP2001326429A (ja) * 2000-05-17 2001-11-22 Sony Corp プリント配線基板
JP3488888B2 (ja) * 2000-06-19 2004-01-19 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ用回路基板の製造方法及びそれを用いた半導体パッケージ用回路基板
US6507100B1 (en) * 2000-06-28 2003-01-14 Advanced Micro Devices, Inc. Cu-balanced substrate
US6380633B1 (en) 2000-07-05 2002-04-30 Siliconware Predision Industries Co., Ltd. Pattern layout structure in substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111526678A (zh) * 2020-04-28 2020-08-11 维沃移动通信(重庆)有限公司 电子设备的壳体及电子设备

Also Published As

Publication number Publication date
US20050145413A1 (en) 2005-07-07
TWI229574B (en) 2005-03-11
US20040084205A1 (en) 2004-05-06
US7266888B2 (en) 2007-09-11
US6864434B2 (en) 2005-03-08

Similar Documents

Publication Publication Date Title
TW200408319A (en) Warpage-preventing circuit board and method for fabricating the same
TW564533B (en) Warpage-preventing substrate
JP3619773B2 (ja) 半導体装置の製造方法
KR100212607B1 (ko) 반도체 칩 팩키지
TWI646642B (zh) 晶片封裝結構及其製造方法
TW201537719A (zh) 堆疊型半導體封裝
US9258890B2 (en) Support structure for stacked integrated circuit dies
TWI754785B (zh) 積體電路封裝以及用於製造積體電路封裝的方法
TWI550791B (zh) 半導體封裝件及其製法
JP5404513B2 (ja) 半導体装置の製造方法
TWI615925B (zh) 半導體裝置
CN106847780B (zh) 框架具有多个臂的半导体器件及相关方法
TW554501B (en) Substrate for semiconductor package
JP2004289156A (ja) リセスボンド半導体パッケージ基板
CN114496973A (zh) 电子封装件及其线路结构
TW201904011A (zh) 電子封裝件及其製法
JP2004247464A (ja) 半導体装置及びその製造方法
TWI621223B (zh) 電子封裝件及其製法
CN103137498B (zh) 半导体封装结构及其制作方法
CN1276504C (zh) 一种防止翘曲现象发生的基板
CN1306602C (zh) 可防止热变形的电路板及其制法
JP2002270725A (ja) 半導体装置およびその製造方法
JPH0241906B2 (zh)
JP5587464B2 (ja) 半導体装置の製造方法
JP2002270726A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent