200405152 玖、發明說明： 發明所屬夕枝術領域 本發明是有關於一種非接觸式積體電路（IC)卡’且較 特別的是，有關於用來從所接收到的射頻訊號產生一時脈 訊號，以及將資料復原在非接觸式積體電路卡的一種電 路。 先前技術 自從信用卡在1920年代開始問世以來，目前已經發 展出多種電子資訊卡，如銀行卡（debit cards)(或現金卡）、 信用卡、識別卡、百貨公司會員卡、等等。近來，因整合 一迷你電腦至其卡上而得名的積體電路（integrated circuit， 簡稱1C)卡，因其便利性、穩定性、以及廣大應用範圍， 已經相當普遍。 一般而言，積體電路卡係爲一輕薄半導體元件附著於 如信用卡大小的一塑膠卡片上的卡片型狀。與包含磁條的 傳統信用卡相比較，積體電路卡具有高穩定性、寫入資料 保護、以及高完全性等優點。因此，積體電路卡已經被廣 泛接受，成爲下一世代的多媒體資訊媒體。 積體電路卡可大略分爲接觸式積體電路卡、非接觸式 積體電路卡（Contactless IC Card，簡稱CICC)、以及遠地耦 合通訊卡（Remote Coupling Communication Card，簡稱 RCCC)三種。ISO(國際標準制定組織）與IEC(國際電氣技 術委員會）已經制定一個國際化標準的用來與CICC連繫的 專用系統。特定的國際標準IS0/IEC 14443指定其類似卡 12229pif.doc/008 5 200405152 的物理特性、射頻功率及訊號介面、啓動及反碰撞、以及 傳輸協定。在ISO/IEC 14443的標準之下，非接觸式積體 電路卡與執行資料處理和/或記憶體功能的一積體電路結 合在一起。非接觸式卡技術的成功是拜藉由與一近似耦合 元件耦和的一感應器（也就是一讀卡機）交換訊號，以及不 用電池（galvanic element)(缺乏從外部介面裝置至卡片所包 含的積體電路的一電阻路徑），就能將電源供應至卡片的 技術成熟之賜。讀卡機產生一個與卡片耦合的射頻（radio frequency，RF)能量場，以用來傳送能量，以及做爲通訊的 調變之用。射頻工作場的頻率fc爲13.56MHz±7kHz。 第1A圖和第1B圖係顯示IS0/IEC 14443的A型及 B型介面通訊訊號的槪念。第1A圖的通訊訊號是從一讀 卡機傳送到一非接觸式積體電路卡，而第1B圖的通訊訊 號則是從非接觸式積體電路卡傳送到讀卡機。IS0/IEC 14443協定說明A型及B型兩種通訊訊號介面。當使用A 型通訊訊號介面時，從讀卡機到非接觸式積體電路卡的通 訊，是使用射頻工作場的ASK 100%的調變原理，以及一 個修正式米勒碼（Modified Miller)原理。從讀卡機到非接 觸式積體電路卡的傳輸位兀率爲fc/128，也就是 106Kbps(千位元/秒）。從非接觸式積體電路卡到讀卡機的 傳輸，是使用曼徹斯特碼（Manchester code)原理先編碼， 然後再用On-Off Key(OOK)原理調變。目前在韓國漢城的 地下鐵及巴士中由A型通訊訊號介面所管理的卡片，是使 用從讀卡機所接收到的一個ASK-調變訊號，產生一固定 12229pif.doc/008 200405152 時間週期的時序（timing)，並且一次接收及傳送一位元的 資料。 將資料從一個積體電路卡傳送到讀卡機時，會從讀卡 機穩定地提供電力給積體電路卡。然而，當資料從讀卡機 傳送到積體電路卡時，會產生如第2圖所示的一個暫停週 期t2。也就是說，從積體電路卡到讀卡機的傳輸電力，每 一個暫停週期t2期間都會被中斷一次。射頻接收器所產 生的一個時脈訊號，在該時間會有不連續波形產生。在此 情況下，因爲用來傳送及接收的同步時脈訊號，是藉由分 頻像這樣的具有不連續週期的時脈訊號而產生，所以很難 維持ISO/IEC 14443A型協定所需的i〇6Kbps的特定傳輸 位元率。 第3A圖和第3B圖係顯示ISO/IEC 14443的A型資 料的資料訊框（data frames)。第3A圖係顯示一個用來啓動 通訊的短訊框，包括一個用來啓動通訊的訊號S、以最低 有效位兀（LSB)爲首依次傳送的7個資料位元bl-b7、以及 一個用來結束通訊的訊號E。第3B圖係繪示一個用來作 爲資料交換的標準訊框，包括一個啓動通訊S、8個資料 位元加上奇數奇偶性位元（odd parity bits)bl-b7及P，以及 結束通訊E。而且每一位元組的最低有效位元會先被傳送。 接在每一位元組之後是一個奇數奇偶性位元P。該奇偶性 位元P設定成使得1的個數爲奇數(bl到b8及P)。 一個在非接觸式積體電路卡中的習知解碼電路，會從 與一同步時脈訊號相同步，而接收的一射頻訊號中，擷取 12229pif.doc/008 7 200405152 對應位元，將所擷取的位元分頻成一啓動位元s、資料位 元bl-b7及一結束位兀E’並且偵測從分頻位元資訊所接 收的資料。爲使解碼電路正常工作，必須具有不包含不連 續週期（也就是一暫停週期）的同步時脈訊號。 因此，非接觸式積體電路卡技術需要從具有如第2圖 所示的不連續或具暫停週期t2的一個射頻訊號中，產生 一固定頻率的同步時脈訊號。 發明內容 有鑑於此，本發明提供一種在一個非接觸式積體電路 卡中，可以從一個所接收到的射頻訊號，產生一固定頻率 的同步時脈訊號，而不會具有一暫停週期的電路。 在一個非接觸式積體電路裝置中，用來產生一時脈訊 號以及用來解碼資料的裝置包括：一個接收器，用來接收 具有一暫停週期的一射頻訊號；一個分頻器（divider)，用 來分頻所接收到的射頻訊號，以提供一分頻訊號；一個第 一計數器，用來計算在所接收到的射頻訊號的每一非暫停 週期上的分頻訊號週期；一個第二計數器，用來計算分頻 訊號週期；以及一個解碼器，響應第一及第二計數器的輸 出，產生一同步時脈訊號以及一解碼資料訊號，其中該第 二計數器是由該同步時脈訊號所重置（reset)。 根據本發明一方面，第一計數器是在射頻訊號的暫停 週期期間所重置。 根據本發明一方面，第二計數器是在同步時脈訊號的 下降邊緣時所重置。 12229pif.doc/008 8 200405152 根據本發明一方面，射頻訊號是遵循ISO-14443 A型 介面標準。 根據本發明一方面，解碼器更加包括響應第一及第二 計數器的輸出，產生一用來指示所接收到訊框結束的訊 號。 本發明另一目的是提供一種在一非接觸式積體電路卡 中，可精確地復原從所接收到的射頻訊號中所取得的資料 的電路。 在一個非接觸式積體電路卡中，用來當做資料復原的 裝置包括：一個接收器，用來接收具有一暫停週期的一射 頻訊號，以及從所接收的射頻訊號中，擷取資料及時脈訊 號；一個分頻器，用來分頻時脈訊號，以產生一個分頻時 脈訊號；一個第一計數器，用來計算在資料訊號的每一非 暫停週期上的分頻時脈訊號週期；一個第二計數器，用來 計算分頻時脈訊號週期；以及一個解碼器，響應第一及第 二計數器的輸出，產生一同步時脈訊號以及一解碼資料訊 號，其中該第二計數器是由該同步時脈訊號所重置。 根據本發明另一方面，第一計數器是在資料訊號的暫 停週期開始時所重置。第一計數器較偏好爲一 3位元計數 益1。弟一目十數益較偏好是在同步時脈訊號的下降邊緣時所 重置。第二計數器可爲一 2位元計數器。 第二計數器的輸出較偏好爲在，0,與，2’之間順序變 換。 第一計數器較偏好爲一 4位元計數器。第二計數器可 12229pif.doc/008 200405152 藉由第一及第二計數器的輸出組合所重置。第二計數器亦 可爲一 3位兀計數器。 解碼器較偏好更加包括響應第一及第二計數器的輸 出，產生一用來指示所接收到訊框結束的訊號。 該裝置較偏好更加包括一個或閘（OR gate)，用來接收 用以重置卡片的一重置訊號及該資料訊號，其中第一計數 器是藉由或閘的輸出所重置。 分頻器更加包括複數個在輸入端點及輸出端點之間串 聯的分頻單元，其中輸入端點接收來自接收器的時脈訊 號，而且每一分頻單元將一輸入訊號分頻成N份(N爲一 整數）；以及一個選擇器，響應一外部選擇訊號，選擇該 些分頻單元的其中一輸出，當成該分頻時脈訊號。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特以較佳實施例，並配合所附圖式，作詳細 說明如下： 實施方式: 以下將參考所附繪圖，詳細說明本發明的較佳實施 例。 第4圖係顯示根據本發明的一個非接觸式積體電路卡 的時脈產生及資料復原電路的單元圖。請參考第4圖所示， 合倂到一非接觸式積體電路卡的時脈產生及資料復原電 路，包括一個射頻單元110、一個時脈分頻器120、一個 或閘130、一個3位元計數器140、一個2位元計數器150、 一個時脈產生器與解碼器單元160、以及一個重置控制器 12229pif.doc/008 10 200405152 170 〇 射頻單元110接收一個例如像是根據ISO/IEC 14443 A 型協定，頻率爲13·56ΜΗζ，傳輸位元率爲106Kbps的射 頻訊號，並且將所接收到的訊號，轉換成適用於數位電路 的一時脈訊號RF_CLK及一資料訊號RF_IN。時脈分頻器 120將單元110所輸出的時脈訊號RF_CLK分頻，以產生 一分頻時脈訊號DIV_CLK。如下所述，時脈分頻器120 響應一選擇訊號SEL，產生各種頻率的時脈訊號，並且輸 出該些時脈訊號的其中之一。或閘130從單元110接收 一系統重置訊號SYS_RST及資料訊號RF_IN。 請繼續參考第4圖所示，3位元計數器140是由或閘 130的輸出所重置，並且計算從時脈分頻器所輸出的分頻 時脈訊號DIV_CLK的週期。3位元計數器140的輸出 RX—IN—CNT3會在，0,到’7,（以二進位數字，從，000,到，111，) 之間順序變換。2位元計數器150是由重置控制器170所 產生的一個重置訊號RST所重置，並且計算從時脈分頻器 120所輸出的分頻時脈訊號DIV_CLK的週期。2位元計數 器150的輸出STATE_CNT2會在’0’到’2’(以二進位數字， 從’00’到’10’)之間順序變換。 時脈產生器與解碼器單元160爲響應計數器140及150 的輸出RX_IN—CNT3及STATE_CNT2動作，並且產生一 個同步時脈訊號ETU_RX_CLK、一個解碼資料訊號 RX—IN、以及一個訊框結束訊號END—OF—RX〇重置控芾[J 器170是由系統重置訊號SYS_RST所重置，並且響應同 12229pif.doc/008 11 200405152 步時脈訊號etu_rx_clk，產生重置訊號RST。 第5圖係顯示使用一短訊框來啓動通訊的如第4圖所 示的電路的各種訊號的響應及操作時序圖。以下將參考第 4圖和第5圖，詳細說明時脈產生與資料復原電路的操作 細節。 請參考第4圖和第5圖所示，在從一讀卡機（未繪示) 接收一短訊框之前，3位元計數器140及重置控制器170， 會由一系統重置訊號SYSJRST所重置。此刻，2位元計數 器150會由重置控制器170所輸出的一重置訊號RST所重 置。當執行重置時，計數器140及150的輸出値 RX_IN—CNT3及STATE_CNT2會變成，0’。如第5圖所示， 在接收短訊框之前，射頻單元U0會輸出一個高位準的資 料訊號RF_IN。 當接收到短訊框當成一啓動位元S的一第一位元時， 從射頻單元110所輸出的資料訊號RF_IN，會從高位準(邏 輯’Γ)變換到低位準（邏輯’〇’）。此刻，時脈分頻器120開 始分頻時脈訊號RF_CLK。假設繪示在第3A圖中的短訊 框的每一位兀的週期爲一個ETU(基本時間單位），則在本 實施例中，時脈分頻器120所輸出的分頻時脈訊號200405152 发明 Description of the invention: The field of the invention belongs to a non-contact integrated circuit (IC) card, and more particularly, it is used to generate a clock signal from a received radio frequency signal And a circuit for restoring data in a non-contact integrated circuit card. Prior art Since the introduction of credit cards in the 1920s, a variety of electronic information cards have been issued, such as debit cards (or cash cards), credit cards, identification cards, department store membership cards, and so on. Recently, an integrated circuit (1C) card, which is named for integrating a mini computer into its card, has become quite common due to its convenience, stability, and wide range of applications. Generally speaking, the integrated circuit card is a card shape in which a thin and light semiconductor element is attached to a plastic card, such as a credit card. Compared with traditional credit cards containing magnetic stripes, integrated circuit cards have the advantages of high stability, data protection, and high integrity. Therefore, integrated circuit cards have been widely accepted as the next generation of multimedia information media. Integrated circuit cards can be roughly divided into three types: contact integrated circuit cards, contactless IC cards (CICC), and remote coupling communication cards (RCCC). ISO (International Standards Development Organization) and IEC (International Electrotechnical Commission) have developed an international standard for a dedicated system to connect with CICC. The specific international standard IS0 / IEC 14443 specifies its physical characteristics similar to the card 12229pif.doc / 008 5 200405152, RF power and signal interface, startup and anti-collision, and transmission protocols. Under the ISO / IEC 14443 standard, contactless integrated circuit cards are combined with an integrated circuit that performs data processing and / or memory functions. The success of contactless card technology is through the use of a sensor (that is, a card reader) coupled with an approximate coupling element and the use of a battery (galvanic element) (the lack of external interface devices to the card contains (A resistor path of the integrated circuit), which can supply power to the card due to the mature technology. The card reader generates a radio frequency (RF) energy field that is coupled to the card to transmit energy and to modulate communications. The frequency fc of the RF working field is 13.56MHz ± 7kHz. Figures 1A and 1B show the idea of the type A and B interface communication signals of IS0 / IEC 14443. The communication signal in Fig. 1A is transmitted from a card reader to a non-contact integrated circuit card, and the communication signal in Fig. 1B is transmitted from a non-contact integrated circuit card to a card reader. The IS0 / IEC 14443 protocol describes two types of communication signal interfaces: type A and type B. When using the A-type communication signal interface, the communication from the card reader to the non-contact integrated circuit card is based on the 100% modulation principle of the ASK in the RF workplace and a modified Miller principle . The transmission bit rate from the card reader to the non-contact integrated circuit card is fc / 128, which is 106Kbps (kilobits per second). The transmission from the contactless integrated circuit card to the card reader is first encoded using the Manchester code principle and then modulated using the On-Off Key (OOK) principle. At present, the cards managed by the A-type communication interface in subways and buses in Seoul, South Korea use an ASK-modulation signal received from the card reader to generate a fixed 12229pif.doc / 008 200405152 time period. Timing, and receiving and transmitting one bit of data at a time. When data is transferred from an integrated circuit card to a card reader, power is stably supplied from the card reader to the integrated circuit card. However, when data is transferred from the card reader to the integrated circuit card, a pause period t2 as shown in Fig. 2 is generated. In other words, the power transmission from the integrated circuit card to the card reader is interrupted once during each pause period t2. A clock signal generated by the RF receiver will have a discontinuous waveform at that time. In this case, because the synchronous clock signal used for transmission and reception is generated by dividing a clock signal with a discontinuous period such as this, it is difficult to maintain the i required by the ISO / IEC 14443A type protocol. 〇6Kbps specific transmission bit rate. Figures 3A and 3B show the data frames of ISO / IEC 14443 Type A data. Figure 3A shows a short message box for starting communication, including a signal S for starting communication, 7 data bits bl-b7 transmitted in order starting with the least significant bit (LSB), and a Signal E to end communication. Figure 3B shows a standard frame for data exchange, including a start communication S, 8 data bits plus odd parity bits bl-b7 and P, and end communication E . And the least significant bit of each byte is transmitted first. Following each byte is an odd-even parity bit P. The parity bit P is set so that the number of 1 is an odd number (bl to b8 and P). A conventional decoding circuit in a non-contact integrated circuit card will synchronize with a synchronous clock signal and receive a radio frequency signal, which will capture 12229pif.doc / 008 7 200405152 corresponding bits, The fetched bits are divided into an enable bit s, a data bit bl-b7, and an end bit E ′, and the data received from the divided bit information is detected. In order for the decoding circuit to work properly, it must have a synchronous clock signal that does not include discontinuous periods (that is, a pause period). Therefore, the contactless integrated circuit card technology needs to generate a fixed-frequency synchronous clock signal from a radio frequency signal having a discontinuity as shown in FIG. 2 or with a pause period t2. SUMMARY OF THE INVENTION In view of this, the present invention provides a circuit in a non-contact integrated circuit card that can generate a fixed-frequency synchronous clock signal from a received radio frequency signal without a pause period. . In a non-contact integrated circuit device, a device for generating a clock signal and for decoding data includes: a receiver for receiving a radio frequency signal having a pause period; a divider, Used to divide the received RF signal to provide a divided signal; a first counter is used to calculate the divided signal period on each non-pause period of the received RF signal; a second counter , Used to calculate the frequency division signal period; and a decoder, in response to the output of the first and second counters, generates a synchronous clock signal and a decoded data signal, wherein the second counter is weighted by the synchronous clock signal Reset (reset). According to an aspect of the invention, the first counter is reset during a pause period of the radio frequency signal. According to an aspect of the present invention, the second counter is reset when the falling edge of the clock signal is synchronized. 12229pif.doc / 008 8 200405152 According to one aspect of the present invention, the radio frequency signal complies with the ISO-14443 Type A interface standard. According to an aspect of the present invention, the decoder further includes generating a signal for indicating the end of the received frame in response to the outputs of the first and second counters. Another object of the present invention is to provide a circuit capable of accurately recovering data obtained from a received radio frequency signal in a non-contact integrated circuit card. In a non-contact integrated circuit card, the device for data recovery includes: a receiver for receiving a radio frequency signal with a pause period, and acquiring data and time pulses from the received radio frequency signal Signal; a frequency divider for dividing the clock signal to generate a frequency dividing clock signal; a first counter for calculating the frequency division clock signal period at each non-pause period of the data signal; A second counter for calculating the frequency division clock signal period; and a decoder, in response to the output of the first and second counters, generating a synchronous clock signal and a decoded data signal, wherein the second counter is generated by the The sync clock signal is reset. According to another aspect of the invention, the first counter is reset at the beginning of the pause period of the data signal. The first counter prefers a 3-bit count. My brother's preference is reset at the falling edge of the synchronous clock signal. The second counter may be a 2-bit counter. The output of the second counter is preferred to be sequentially changed between, 0, and, 2 '. The first counter is preferably a 4-bit counter. The second counter can be reset by 12229pif.doc / 008 200405152 by the output combination of the first and second counters. The second counter may also be a 3-bit counter. The decoder more preferably includes responding to the output of the first and second counters to generate a signal indicating the end of the received frame. The device more preferably includes an OR gate for receiving a reset signal for resetting the card and the data signal, wherein the first counter is reset by the output of the OR gate. The frequency divider further includes a plurality of frequency division units connected in series between the input endpoint and the output endpoint. The input endpoint receives a clock signal from the receiver, and each frequency division unit divides an input signal into N. (N is an integer); and a selector, in response to an external selection signal, selecting one of the output of the frequency division units as the frequency division clock signal. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes in detail the preferred embodiments in conjunction with the accompanying drawings as follows: Embodiments: The following drawings will be referred to the accompanying drawings, The preferred embodiments of the present invention will be described in detail. Fig. 4 is a unit diagram showing a clock generation and data recovery circuit of a non-contact integrated circuit card according to the present invention. Please refer to Figure 4, the clock generation and data recovery circuit combined with a non-contact integrated circuit card includes a radio frequency unit 110, a clock divider 120, an OR gate 130, and a 3-bit A meta counter 140, a 2-bit counter 150, a clock generator and decoder unit 160, and a reset controller 12229pif.doc / 008 10 200405152 170 〇 The radio frequency unit 110 receives a signal such as, for example, according to ISO / IEC 14443 Type A protocol, with a frequency of 13.56MHz and a transmission rate of 106Kbps, and converts the received signal into a clock signal RF_CLK and a data signal RF_IN suitable for digital circuits. The clock frequency divider 120 divides the clock signal RF_CLK output by the unit 110 to generate a frequency-divided clock signal DIV_CLK. As described below, the clock frequency divider 120 generates a clock signal of various frequencies in response to a selection signal SEL, and outputs one of the clock signals. The OR gate 130 receives a system reset signal SYS_RST and a data signal RF_IN from the unit 110. Please continue to refer to FIG. 4, the 3-bit counter 140 is reset by the output of the OR gate 130, and calculates the period of the divided clock signal DIV_CLK output from the clock divider. The output RX_IN_CNT3 of the 3-bit counter 140 will be sequentially changed from 0, to '7, (in binary numbers, from 000, to, 111,). The 2-bit counter 150 is reset by a reset signal RST generated by the reset controller 170, and calculates the period of the frequency-divided clock signal DIV_CLK output from the clock frequency divider 120. The output STATE_CNT2 of the 2-bit counter 150 is sequentially changed from '0' to '2' (in binary numbers, from '00' to '10'). The clock generator and decoder unit 160 operates in response to the outputs RX_IN_CNT3 and STATE_CNT2 of the counters 140 and 150, and generates a synchronous clock signal ETU_RX_CLK, a decoded data signal RX_IN, and a frame end signal END_OF. —RX〇 Reset control [J device 170 is reset by the system reset signal SYS_RST, and responds to the same clock signal etu_rx_clk as 12229pif.doc / 008 11 200405152, and generates a reset signal RST. Fig. 5 is a timing chart showing the response and operation of various signals of the circuit shown in Fig. 4 using a short message box to initiate communication. The operation details of the clock generation and data recovery circuit will be described in detail below with reference to FIGS. 4 and 5. Please refer to Figure 4 and Figure 5. Before receiving a short message frame from a card reader (not shown), the 3-bit counter 140 and the reset controller 170 will be reset by a system SYSJRST. Reset. At this moment, the 2-bit counter 150 is reset by a reset signal RST output from the reset controller 170. When a reset is performed, the outputs 计数器 RX_IN_CNT3 and STATE_CNT2 of the counters 140 and 150 become 0 '. As shown in Figure 5, before receiving the short message frame, the radio frequency unit U0 will output a high-level data signal RF_IN. When the short message frame is received as a first bit of an enable bit S, the data signal RF_IN output from the radio frequency unit 110 will be transformed from a high level (logic 'Γ) to a low level (logic' 0 '). . At this moment, the clock frequency divider 120 starts to divide the clock signal RF_CLK. Assuming that the period of each bit of the short message frame shown in FIG. 3A is an ETU (basic time unit), in this embodiment, the frequency division clock signal output by the clock frequency divider 120
ETU DIV_CLK的週期爲 4 。 在重置之後，計數器140及150會響應分頻時脈訊號 DIV_CLK的下降邊緣，執行一計數動作。當計數器140 及150的輸出RX_IN_CNT3及STATE_CNT2具有特定値 12229pif.doc/008 200405152 時，時脈產生器與解碼器單元160會產生一個同步時脈訊 號ETU_RX_CLK的上升及下降邊緣。 下列的表格係顯示響應計數器！4〇及150的輸出 RX_IN_CNT3及STATE_CNT2，產生同步時脈訊號 ETU_RX_CLK的各種條件。 第1表 ETU_RX_CLK RX_IN_CNT3 STATECNT2 [〇] [〇] 0 0 0 1 1 1 上升時脈 2 1 4 1 5 1 6 1 0 2 2 0 2 2 下降時脈 3 0 4 0 6 0 7 0 舉例來說，當3位元計數器140的輸出RX_IN_CNT3 爲1，而且2位元計數器150的輸出STATE_CNT2亦爲1 12229pif.doc/008 13 200405152 時，會建立同步時脈訊號ETU_RX_CLK的一個上升邊緣。 當3位元計數器140的輸出RX_IN—CNT3爲2，而且2位 元計數器150的輸出STATE_CNT2亦爲2時，會建立同步 時脈訊號ETU_RX_CLK的一個下降邊緣。 第4圖的重置控制器170會響應從時脈產生器與解碼 器單元160所輸出的同步時脈訊號ETU_RX_CLK的一下 降邊緣，啓動一重置訊號RST。2位元計數器150會由啓 動該重置訊號RST所重置。當從射頻單元110所輸出的資 料訊號RF_IN，從高位準變成低位準時，3位元計數器140 就會被重置。重覆執行上述動作，就會產生頻率爲o.llMHz 的同步時脈訊號ETU_RX_CLK。 此刻，響應計數器140及150的輸出RX_IN_CNT3 及STATE_CNT2，時脈產生器與解碼器單元160會產生一 個解碼資料訊號RX_IN。The period of ETU DIV_CLK is 4. After resetting, the counters 140 and 150 will perform a counting operation in response to the falling edge of the divided clock signal DIV_CLK. When the outputs RX_IN_CNT3 and STATE_CNT2 of the counters 140 and 150 have a specific 値 12229pif.doc / 008 200405152, the clock generator and decoder unit 160 will generate a synchronous clock signal ETU_RX_CLK rising and falling edges. The following table shows the response counters! The outputs RX_IN_CNT3 and STATE_CNT2 of 40 and 150 generate various conditions of the synchronous clock signal ETU_RX_CLK. Table 1 ETU_RX_CLK RX_IN_CNT3 STATECNT2 [〇] [〇] 0 0 0 1 1 1 rising clock 2 1 4 1 5 1 6 1 0 2 2 0 2 2 falling clock 3 0 4 0 6 0 7 0 For example, When the output RX_IN_CNT3 of the 3-bit counter 140 is 1, and the output STATE_CNT2 of the 2-bit counter 150 is also 1 12229pif.doc / 008 13 200405152, a rising edge of the synchronous clock signal ETU_RX_CLK will be established. When the output RX_IN_CNT3 of the 3-bit counter 140 is 2, and the output STATE_CNT2 of the 2-bit counter 150 is also 2, a falling edge of the synchronous clock signal ETU_RX_CLK is established. The reset controller 170 of FIG. 4 will start a reset signal RST in response to the falling edge of the synchronous clock signal ETU_RX_CLK output from the clock generator and decoder unit 160. The 2-bit counter 150 is reset by activating the reset signal RST. When the data signal RF_IN output from the radio frequency unit 110 changes from a high level to a low level, the 3-bit counter 140 is reset. Repeatedly performing the above operation will generate a synchronous clock signal ETU_RX_CLK with a frequency of o.llMHz. At this moment, in response to the outputs RX_IN_CNT3 and STATE_CNT2 of the counters 140 and 150, the clock generator and decoder unit 160 will generate a decoded data signal RX_IN.
下列的表格係顯示響應計數器140及150的輸出 RX_IN_CNT3及STATE_CNT2，產生解碼資料訊號RX_IN 的各種條件。 第2表 RF—IN RX_IN_CNT3 STATECNT2 1 ETU LOGIC 0 2 2 0111 4 0 1111 5 2 7 2 0 2 LOGIC 1 3 0 1101 7 0 12229pif.doc/008 14 200405152 資料訊號RF—IN係爲修正型米勒碼，當在一 ETU期 間，其値爲’0111’或’11U，，代表邏輯，〇,，而在一 ETU期 間’其値爲’1101’，則代表邏輯，丨，。舉例來說，當計數器 140的輸出RX—IN—CNT3爲〇,而且計數器15〇的輸出 STATE—CNT2爲2時，單元ι6〇會輸出具高位準的解碼資 料訊號RX—IN。當計數器14〇的輸出rX_in—CNT3爲4， 而且計數器15〇的輸出STATE_CNT2爲〇時，單元160會 輸出具低位準的解碼資料訊號RX_IN。根據該條件，所接 收到的資料RFJN ”llii0111〇11111〇1，，，會被轉換成解碼 資料 RX_IN ”0001”。 以下說明用來偵測指示訊框結束的一結束位元E的方 法。響應計數器140及15〇的輸出RX—IN—CNT3及 STATE_CNT2，單元 160產生一個訊框結束訊號 END_OF_RX。下列的表格係顯示響應計數器140及150 的輸出RX_IN_CNT3及STATE_CNT2，產生訊框結束訊號 END_OF_RX的各種條件。 第3表 RXIN RXIN—CNT3 一 STATE_CNT2 ENDOFRX 6 0 0 7 如第3表所示，當3位元計數器140的輸出 RX_1N_CNT3爲6或7，而且2位元計數器150的輸出 STATE_CNT2爲0時，時脈產生器與解碼器單元160會啓 15 12229pit'.doc/008 200405152 動位於高位準的訊框結束訊號END_〇F_RX。 以相同方式，本發明可藉由產生一 0.11MHz的同步 時脈訊號ETU_RX_CLK以及一解碼資料訊號RX__IN，而 接收適用於ISO/IEC 14443 A型協定的資料。 雖然本發明說明的範例是使用106Kbps位元率，但本 發明亦可支援各種位元率。第6圖係繪示一個第4圖所示 的時脈分頻器120的實施例範例。請參考第4圖所示，時 脈分頻器120包括複數個分頻器(或分頻單元）121-127，以 及一個位元率選擇器128。分頻器121-127是串聯在輸入 端點120a及輸出端點120b之間。每一分頻器121-127將 所接收到訊號的頻率除以二。位元率選擇器128選擇分頻 器121-127的分頻時脈訊號ETUD2-TUD64的其中之一， 當成一個輸出DIV_CLK。 根據ISO/IEC 14443標準，時脈訊號RF_CLK的頻率 爲13.56MHz。爲支援106Kbps的位元率，從分頻器125 所輸出的時脈訊號ETUD4，被用來當成一時脈訊號 DIV_CLK，並且將其供應至2位元計數器140及3位元計 數器150，以及時脈產生器與解碼器單元160。舉例來說， 爲支援212Kbps的位元率，從分頻器124所輸出的時脈訊 號ETUD8，會被用來當成一時脈訊號DIV_CLK，並且將 其供應至2位元計數器140及3位元計數器150，以及時 脈產生器與解碼器單元160。因此，根據本發明的時脈產 生與資料復原電路可支援3.2Mbps的位元率。 如上所述，當積體電路卡趨近讀卡機（終端機）時，從 12229pif.doc/008 200405152 讀卡機傳送到積體電路卡的射頻訊號的暫停週期就會改 變。像這樣的暫停週期是會根據讀卡機與積體電路卡之間 的距離、天線的匹配阻抗、或射頻訊號的強度而變化。只 有在該暫停週期是設定爲如第2圖所示的最小値〜最大値 範圍中的某一設定値時’如第4圖所示的非接觸式積體電 路卡的時脈產生與資料復原電路才會正常工作。當該暫停 週期在最小値〜最大値範圍中變化時，電路100可能無法 復原正確碼。其原因係爲計數器150是以2位元的方式計 數，因此限制其在一單位週期之內，只有25%的解析度。 第7圖係顯示根據本發明另一實施例的一種非接觸式 積體電路卡的時脈產生及資料復原電路的功能單元圖。 請參考第7圖所示，除了計數器240是以4位元的方 式計數，而且計數器250是以3位元的方式計數以外’時 脈產生與資料復原電路200，係與第4圖所示的電路1〇〇 相似。此外，時脈產生與解碼電路260還會提供一個用來 重置計數器250的訊號。 當資料訊號RF_IN爲高位準時，4位元計數器240係 與由時脈分頻器220所分頻的時脈訊號DIV_CLK的上升 及下降邊緣同步，並且產生一個輸出RX_IN_CNT4。而當 資料訊號RFJN爲低位準時，4位元計數器240會重置。 從4位元計數器240所輸出的RX_IN_CNT4，會在，〇〇〇〇, 到’1111’(從0到15)之間順序變動。響應時脈產生與解碼 電路260所輸出的一淸除訊號CLEAR，3位元計數器250 會重置。3位元計數器250係與由時脈分頻器22〇所分頻 12229pif.doc/008 17 200405152 的時脈訊號DIV_CLK的上升及下降邊緣同步，並且產生 一個輸出STATE_CNT3。而且從3位元計數器250所輸出 的STATE—CNT3，會在’000’到’111’(從·0到7)之間順序變 動。 響應輸出訊號RX_IN_CNT4及STATE_CNT3，時脈 產生與解碼電路260產生一同步時脈訊號，並且產生解碼 資料訊號RX_IN、一個訊框結束訊號END_OF_RX、以及 一個淸除訊號CLEAR。 第8圖係顯示接收一用來啓動通訊條件的短訊框訊號 的電路的操作時序圖。 請參考第7圖和第8圖所示，在從讀卡機（未繪示）接 收到一短訊框之前，計數器24及電路260會由一系統重 置訊號SYS_RST所重置。計數器250是由時脈產生與解 碼電路260所輸出的淸除訊號CLEAR所重置，使計數器 240下降邊緣元250的啓始輸出變爲零。此刻，射頻單元 210輸出一高位準的資料訊號RF_IN。如果接下來接收到 第一位元S，則射頻區塊210所產生的資料訊號RF_IN， 會從高位準變成高低位準。從此刻起，時脈分頻器220開 始執行頻率分頻動作。從時脈分頻器220所輸出的分頻時 脈訊號DIV_CLK的週期時間係爲1/4 ETU。 每當碰到分頻時脈訊號DIV_CLK的上升及下降邊緣 時，計數器240及250就會往上加一。時脈產生與解碼電 路260接收計數器240及250的輸出，並且當輸出符合特 定的預設値時，建立同步時脈訊號ETU_RX_CLK的上升 12229pif.doc/008 18 200405152 及下降邊緣。以下的第4表綜合整理根據計數器240及250 的輸出，從電路260所產生的同步時脈訊號ETU_RX_CLK 的各種不同圖案（patterns)。 第4表 ETU_RX_CL K RX_IN CNT4 STATE CNT3 Hexa Code [3] [2] [1] [0] [2] [1] [0] RX—IN_CNT4[3 :〇] II STATE_CNT3[2 ：〇] 上升時脈 0 0 0 0 0 1 0 02 0 0 0 1 0 0 1 11 0 1 0 0 0 1 1 43 1 0 0 0 0 1 0 82 1 1 0 0 0 1 0 C2 下降時脈 0 0 0 0 0 0 0 00 0 0 0 1 1 0 0 14 0 0 0 1 1 0 1 15 0 0 0 1 1 1 0 16 0 0 0 1 一 1 1 1 17 0 1 0 0 1 0 0 44 0 1 0 0 1 1 0 46 0 1 0 1 0 0 1 51 0 1 1 0 一0 0 1 61 1 0 0 0 1 1 1 87 1 0 0 1 0 0 1 91 1 0 1 0 0 0 1 A1 1 1 0 0 1 1 0 C6 1 1 0 1 0 0 1 Dl 1 1 1 0 0 0 1 El 19 12229pif.doc/008 200405152 舉例而言，如果計數器240的輸出RX_IN_CNT4爲1， 而且計數器250的輸出STATE_CNT3亦爲1，則會建立同 步時脈訊號ETU_RX_CLK的上升邊緣。如果計數器240 的輸出RX_IN_CNT4爲4，而且計數器250的輸出 STATE_CNT3亦爲4，則會建立同步時脈訊號ETU_RX_CLK 的下降邊緣。因此，可產生位元率爲106Kbps的同步時脈 訊 ETU_RX_CLK。 由計數器240及250的輸出組合所組成的同步時脈訊 號ETU_RX_CLK，亦可由配置在時脈產生與解碼電路260 中的邏輯電路組合裝置所產生。 根據響應同步時脈訊號ETU_RX_CLK的下降邊緣， 由計數器240及250所輸出的RX_IN_CNT4及 STATE_CNT3，時脈產生與解碼電路260會產生資料訊號 RX_IN。 當在一個ETU期間，記數輸出爲0111或1111時， 當成修正米勒碼的資料訊號RF_IN，會變成邏輯0。第5 表綜合整理根據響應同步時脈訊號ETU_RX_CLK的下降 邊緣，由計數器240及250的輸出，產生爲邏輯1的解碼 資料訊號RXJN的各種情形。當計數器240及250的輸 出與第5表中所述不同時，會將資料訊號RX_IN設定成 邏輯0 ◦ 12229pif.doc/008 20 200405152 第5表The following table shows the various conditions of the outputs RX_IN_CNT3 and STATE_CNT2 of the response counters 140 and 150 to generate the decoded data signal RX_IN. Table 2 RF—IN RX_IN_CNT3 STATECNT2 1 ETU LOGIC 0 2 2 0111 4 0 1111 5 2 7 2 0 2 LOGIC 1 3 0 1101 7 0 12229pif.doc / 008 14 200405152 The data signal RF—IN is a modified Miller code When in an ETU, its 値 is '0111' or '11U,' which represents logic, 0, and in an ETU, its 値 is '1101', which means logic, 丨,. For example, when the output RX_IN_CNT3 of the counter 140 is 0 and the output STATE_CNT2 of the counter 150 is 2, the unit ι60 will output a high-level decoding data signal RX_IN. When the output rX_in_CNT3 of the counter 14 is 4 and the output STATE_CNT2 of the counter 15 is 0, the unit 160 will output a decoded data signal RX_IN with a low level. According to this condition, the received data RFJN "llii0111〇11111〇1," will be converted into decoded data RX_IN "0001". The following describes the method for detecting an end bit E indicating the end of the frame. Response The outputs RX_IN_CNT3 and STATE_CNT2 of the counters 140 and 150, the unit 160 generates a frame end signal END_OF_RX. The following table shows the conditions for the outputs RX_IN_CNT3 and STATE_CNT2 of the counters 140 and 150 to generate the frame end signals END_OF_RX Table 3 RXIN RXIN_CNT3_STATE_CNT2 ENDOFRX 6 0 0 7 As shown in Table 3, when the output RX_1N_CNT3 of the 3-bit counter 140 is 6 or 7, and the output STATE_CNT2 of the 2-bit counter 150 is 0, The pulse generator and decoder unit 160 will start 15 12229pit'.doc / 008 200405152 to move the frame end signal END_〇F_RX at a high level. In the same way, the present invention can generate a 0.11MHz synchronous clock signal ETU_RX_CLK and a decoded data signal RX__IN to receive data applicable to the ISO / IEC 14443 Type A protocol. Although the example described in the present invention uses 106Kbps bits However, the present invention can also support various bit rates. Fig. 6 shows an example of the embodiment of the clock frequency divider 120 shown in Fig. 4. Please refer to the clock frequency divider 120 shown in Fig. 4 It includes a plurality of frequency dividers (or frequency division units) 121-127, and a bit rate selector 128. The frequency dividers 121-127 are connected in series between the input endpoint 120a and the output endpoint 120b. Each frequency divider The frequency converter 121-127 divides the frequency of the received signal by two. The bit rate selector 128 selects one of the frequency division clock signals ETUD2-TUD64 of the frequency divider 121-127 as an output DIV_CLK. According to ISO / According to the IEC 14443 standard, the frequency of the clock signal RF_CLK is 13.56MHz. In order to support a bit rate of 106Kbps, the clock signal ETUD4 output from the frequency divider 125 is used as a clock signal DIV_CLK and supplies it to 2 Bit counter 140 and 3-bit counter 150, and clock generator and decoder unit 160. For example, to support a bit rate of 212Kbps, the clock signal ETUD8 output from the frequency divider 124 will be used As a clock signal DIV_CLK and supply it to the 2-bit counter 14 The 0 and 3-bit counters 150, and the clock generator and decoder unit 160. Therefore, the clock generation and data recovery circuit according to the present invention can support a bit rate of 3.2 Mbps. As mentioned above, when the integrated circuit card approaches the card reader (terminal), the pause period of the radio frequency signal transmitted from the card reader to the integrated circuit card will be changed from 12229pif.doc / 008 200405152. The pause period like this will vary depending on the distance between the card reader and the integrated circuit card, the matching impedance of the antenna, or the strength of the RF signal. Only when the pause period is set to a certain range from the minimum value to the maximum value as shown in FIG. 2 'the clock generation and data recovery of the non-contact integrated circuit card shown in FIG. 4 The circuit will work normally. When the pause period is changed from the minimum value to the maximum value, the circuit 100 may fail to recover the correct code. The reason is that the counter 150 is counted in a 2-bit manner, so it is limited to a resolution of 25% within a unit period. FIG. 7 is a functional unit diagram of a clock generation and data recovery circuit of a non-contact integrated circuit card according to another embodiment of the present invention. Please refer to FIG. 7. In addition to the counter 240 counting in a 4-bit manner and the counter 250 counting in a 3-bit manner, the clock generation and data recovery circuit 200 is similar to that shown in FIG. 4. The circuit 100 is similar. In addition, the clock generating and decoding circuit 260 also provides a signal for resetting the counter 250. When the data signal RF_IN is high, the 4-bit counter 240 is synchronized with the rising and falling edges of the clock signal DIV_CLK divided by the clock frequency divider 220, and generates an output RX_IN_CNT4. When the data signal RFJN is at a low level, the 4-bit counter 240 is reset. The RX_IN_CNT4 output from the 4-bit counter 240 changes sequentially from 100,000 to '1111' (from 0 to 15). In response to the CLEAR signal output by the clock generation and decoding circuit 260, the 3-bit counter 250 is reset. The 3-bit counter 250 is synchronized with the rising and falling edges of the clock signal DIV_CLK, which is divided by the clock frequency divider 2220 12229pif.doc / 008 17 200405152, and generates an output STATE_CNT3. Furthermore, the STATE_CNT3 output from the 3-bit counter 250 changes sequentially from '000' to '111' (from · 0 to 7). In response to the output signals RX_IN_CNT4 and STATE_CNT3, the clock generation and decoding circuit 260 generates a synchronous clock signal, and generates a decoded data signal RX_IN, a frame end signal END_OF_RX, and an erasure signal CLEAR. Fig. 8 is a timing chart showing the operation of a circuit that receives a short frame signal for activating communication conditions. Please refer to Figure 7 and Figure 8. Before receiving a short message frame from the card reader (not shown), the counter 24 and circuit 260 will be reset by a system reset signal SYS_RST. The counter 250 is reset by the erasure signal CLEAR output from the clock generating and decoding circuit 260, so that the initial output of the falling edge cell 250 of the counter 240 becomes zero. At this moment, the radio frequency unit 210 outputs a high-level data signal RF_IN. If the first bit S is received next, the data signal RF_IN generated by the radio frequency block 210 will change from a high level to a high level. From this moment, the clock frequency divider 220 starts performing frequency division operation. The cycle time of the frequency-divided clock signal DIV_CLK output from the clock frequency divider 220 is 1/4 ETU. Whenever the rising and falling edges of the divided clock signal DIV_CLK are encountered, the counters 240 and 250 are incremented by one. The clock generation and decoding circuit 260 receives the outputs of the counters 240 and 250, and when the output meets a specific preset threshold, establishes a synchronous clock signal ETU_RX_CLK rising 12229pif.doc / 008 18 200405152 and falling edges. The fourth table below summarizes various patterns of the synchronous clock signal ETU_RX_CLK generated from the circuit 260 according to the outputs of the counters 240 and 250. Table 4 ETU_RX_CL K RX_IN CNT4 STATE CNT3 Hexa Code [3] [2] [1] [0] [2] [1] [0] RX—IN_CNT4 [3: 〇] II STATE_CNT3 [2: 〇] rising clock 0 0 0 0 0 1 0 02 0 0 0 1 0 0 1 11 0 1 0 0 0 1 1 43 1 0 0 0 0 1 0 82 1 1 0 0 0 1 0 C2 falling clock 0 0 0 0 0 0 0 00 0 0 0 1 1 0 0 14 0 0 0 1 1 0 1 15 0 0 0 1 1 1 0 16 0 0 0 1 1 1 1 1 17 0 1 0 0 1 0 0 44 0 1 0 0 1 1 0 46 0 1 0 1 0 0 1 51 0 1 1 0-0 0 1 61 1 0 0 0 1 1 1 87 1 0 0 1 0 0 1 91 1 0 1 0 0 0 1 A1 1 1 0 0 1 1 0 C6 1 1 0 1 0 0 1 Dl 1 1 1 0 0 0 1 El 19 12229pif.doc / 008 200405152 For example, if the output RX_IN_CNT4 of the counter 240 is 1, and the output STATE_CNT3 of the counter 250 is also 1, synchronization will be established. The rising edge of the pulse signal ETU_RX_CLK. If the output RX_IN_CNT4 of the counter 240 is 4, and the output STATE_CNT3 of the counter 250 is also 4, the falling edge of the synchronous clock signal ETU_RX_CLK will be established. Therefore, a synchronous clock ETU_RX_CLK with a bit rate of 106 Kbps can be generated. The synchronous clock signal ETU_RX_CLK composed of the output combinations of the counters 240 and 250 can also be generated by a logic circuit combination device arranged in the clock generation and decoding circuit 260. According to the falling edge of the response synchronous clock signal ETU_RX_CLK, the RX_IN_CNT4 and STATE_CNT3 output by the counters 240 and 250, the clock generation and decoding circuit 260 generates a data signal RX_IN. When the count output is 0111 or 1111 during an ETU, the data signal RF_IN, which is a modified Miller code, will become logic 0. The fifth table comprehensively sorts out various situations of the decoded data signal RXJN of logic 1 from the outputs of the counters 240 and 250 according to the falling edge of the response synchronization clock signal ETU_RX_CLK. When the outputs of counters 240 and 250 are different from those described in Table 5, the data signal RX_IN will be set to logic 0 ◦ 12229pif.doc / 008 20 200405152 Table 5
Signal&RFI N Level RX_IN_CNT4 STATE CNT3 Hexa Code [3] [2] [1] [0] [2] [1] [0] RX—IN_CNT4[3 ··〇] II STATE_CNT3[2 :〇] RX_I N Logic 1 1101 (1ET U) 0 0 0 0 0 1 1 03 0 0 0 0 1 0 0 04 0 0 0 0 1 0 1 05 0 0 0 0 1 1 0 06 0 0 0 1 1 0 0 14 0 0 0 1 1 0 1 15 0 0 0 1 1 1 0 16 0 0 0 1 1 1 1 17 舉例而言，如第8圖所示，如果在同步時脈訊號 ETU_RX_CLK的下降邊緣，計數器240的輸出 RX_IN_CNT4爲0，而且計數器250的輸出STATE—CNT3 爲3，則時脈產生與解碼電路260會產生邏輯1的資料訊 號RX_IN。如果在同步時脈訊號ETU_RX_CLK的下降邊 緣，計數器24〇的輸出RX_IN_CNT4爲8，而且計數器250 的輸出STATE_CNT3爲0，則時脈產生與解碼電路260會 產生邏輯〇的資料訊號RX_IN。以這種方式，可以將，0111 1101 1101 1111 01H 1101”的声料訊號 rF_IN，轉換 21 12229pif.doc/008 200405152 成011001的解碼資料訊號RX—IN。其中，二進位，川刪: 對應於十進位的’26’。 下列的第6表繪示在時脈產生與解碼電路26〇中，用 來產生淸除訊號CLEAR以重置計數器250的碼排列。 第6表 CLEA R RX IN CNT4 STATECNT3 Hexa Code [3] [2] [1] [0] [2] [1] [0] RX—IN_CNT4[3 ··〇] II STATE_CNT3[2 :〇] NOT CLEA R 0 0 0 0 0 0 0 00 X X X X X X X Other case CLEA R 0 0 0 0 0 0 1 01 0 0 0 1 1 0 0 14 0 0 0 1 1 0 1 15 0 0 0 1 1 1 0 16 0 0 0 1 1 1 1 17 0 1 0 0 1 0 0 44 0 1 0 0 1 1 0 46 0 1 0 1 0 0 1 51 0 1 1 0 0 0 1 61 1 0 0 0 1 1 1 87 1 0 0 1 0 0 1 91 1 0 1 0 0 0 1 A1 1 1 0 0 1 1 0 C6 1 1 0 1 0 0 1 D1 1 1 1 0 0 0 1 El 22 I2229pif.doc/008 200405152 如第6表所示，計數器250是由計數器240及250輸 出的邏輯組合所重置。 以下將說明用來識別指示訊框結束的結束彳立元1 E 0勺石馬 排列。時脈產生與解碼電路260，根據如下列第7表所示 的計數器240及250的輸出，產生一個結束訊號 END OF RX。 第7表Signal & RFI N Level RX_IN_CNT4 STATE CNT3 Hexa Code [3] [2] [1] [0] [2] [1] [0] RX—IN_CNT4 [3 ·· 〇] II STATE_CNT3 [2: 〇] RX_I N Logic 1 1101 (1ET U) 0 0 0 0 0 1 1 03 0 0 0 0 1 0 0 04 0 0 0 0 1 0 1 05 0 0 0 0 1 1 0 06 0 0 0 1 1 0 0 14 0 0 0 1 1 0 1 15 0 0 0 1 1 1 0 16 0 0 0 1 1 1 1 17 For example, as shown in Fig. 8, if the falling edge of the synchronous clock signal ETU_RX_CLK is reached, the output RX_IN_CNT4 of the counter 240 is 0, In addition, the output STATE_CNT3 of the counter 250 is 3, and the clock generating and decoding circuit 260 generates a data signal RX_IN of logic 1. If on the falling edge of the synchronous clock signal ETU_RX_CLK, the output RX_IN_CNT4 of the counter 24 is 8 and the output STATE_CNT3 of the counter 250 is 0, the clock generation and decoding circuit 260 will generate a data signal RX_IN of logic 0. In this way, you can convert the audio signal rF_IN of 0111 1101 1101 1111 01H 1101 "into 21 12229pif.doc / 008 200405152 into 011001 decoded data signal RX_IN. Among them, binary, Chuan delete: corresponding to ten Carry '26'. Table 6 below shows the clock generation and decoding circuit 26〇, used to generate the erasure signal CLEAR to reset the code arrangement of the counter 250. Table 6 CLEA R RX IN CNT4 STATECNT3 Hexa Code [3] [2] [1] [0] [2] [1] [0] RX—IN_CNT4 [3 ·· 〇] II STATE_CNT3 [2: 〇] NOT CLEA R 0 0 0 0 0 0 0 00 XXXXXXX Other case CLEA R 0 0 0 0 0 0 1 01 0 0 0 1 1 0 0 14 0 0 0 1 1 0 1 15 0 0 0 1 1 1 0 16 0 0 0 1 1 1 1 17 0 1 0 0 1 0 0 44 0 1 0 0 1 1 0 46 0 1 0 1 0 0 1 51 0 1 1 0 0 0 1 61 1 0 0 0 1 1 1 87 1 0 0 1 0 0 1 91 1 0 1 0 0 0 1 A1 1 1 0 0 1 1 0 C6 1 1 0 1 0 0 1 D1 1 1 1 0 0 0 1 El 22 I2229pif.doc / 008 200405152 As shown in Table 6, counter 250 is a logical combination of counters 240 and 250 output The reset will be described below to identify the end of the indication frame. Ma arrangement. Decode clock generating circuit 260, based on the output as shown in the following Table 7 and 250 of the counter 240, produces an end signal END OF RX. TABLE 7
Signal&RF_ IN Level RX IN_CNT4 STATE—CNT3 Hexa Code [3] [2] [1] [〇] [2] [i] [〇] RX_IN_CNT4 [3：〇] || STATE_CNT3 [2：〇] END_OF_R X 11111111 (2 ETU) 1 1 0 1 1 1 0 D6 1 1 1 1 0 0 1 FI 1 1 1 1 1 0 1 F5 當計數器24〇及MO輸出的邏輯組合如第7表所示 時，時脈產生與解碼電路260就會將訊框結束訊號 END—OF_RX啓動爲高位準。 根據本發明上述的實施例，時脈產生與資料復原電路 2〇〇會產生頻率爲0.11MHz的同步時脈訊號 ETU_RX_CLK，以及解碼資料訊號rXj[N，使其可適用於 接收ISO/IEC 14443 A型協定的資料。 23 12229pif.doc/008 200405152 當資料傳輸率爲106Kbps，而且在時脈訊號的32個 周期期間，出現1位元的資料時，該1位元資料的暫停週 期係爲8個時脈週期。如果暫停週期是落在6到7個時脈 週期的範圍之內，則第4圖所示的電路100可恢復一精確 訊號。在實際操作條件下，當6〜11時脈週期對應於 1.764〜3.234ps時，時脈訊號RF—CLK的暫停週期係爲 0.294〜4.704ps。非接觸式積體電路卡的時脈產生與資料復 原電路200，具有4位元計數器的計數器240，以及3位 元計數器的計數器250，用來追蹤暫停週期的變化。電路 200允許暫停週期在0.884〜4·129μδ的範圍之內變化。對於 212Kbps的資料傳輸率而言，可允許暫停週期在 0.589〜2.604ps的範圍之內變化，而對424Kbps的資料傳 輸率而言，也可允許暫停週期在0.294〜0·884μδ的範圍之 內變化。 如上所述，非接觸式積體電路卡從讀卡機所接收到的 一射頻訊號，產生一個可適用於ISO/IEC 1444 Α型協定的 同步時脈訊號，並且將所接收到的資料訊號解碼。此外， 即使當射頻訊號的暫停週期在一預定範圍中變化時，也可 得到精確的解碼結果。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 圖式簡單說明 12229pif.doc/008 24 200405152 第1A圖和第1B圖係顯示1S0/IEC 14443協定A型 及B型介面的通訊訊號示意圖。 第2圖係顯示從一讀卡機傳送到一積體電路卡的一訊 號波形圖。 第3A圖和第3B圖係顯示ISO/IEC 14443 A型協定的 資料訊框示意圖。 第4圖係顯示根據本發明的一個非接觸式積體電路卡 的時脈產生及資料復原電路的單元圖。 第5圖係顯示第4圖所示的電路的各種訊號的操作時 序圖。 第6圖係顯示第4圖所示的時脈分頻器的一較佳實施 例。 第7圖係顯不根據本發明另一實施例，即使在一暫停 週期期間具大量任務變化，仍可精確復原碼的一種非接觸 式積體電路卡的時脈產生及資料復原電路。 第8圖係顯示第7圖所示的電路的各種訊號的操作時 序圖。 圖式標記說明： 100 :時脈產生與資料復原電路 110 :射頻單元 120 :時脈分頻器 120a :輸入端點 120b :輸出端點 121〜127 :分頻器 12229pif.doc/008 200405152 128 :位元率選擇器 130 :或閘 140 : 3位元計數器 150 : 2位元計數器 160 :時脈產生器與解碼器單元 170 :重置控制器 200 :時脈產生與資料復原電路 210 :射頻單元 220 :時脈分頻器 230 :或閘 240 : 4位元計數器 250 : 3位元計數器 2 6 0 :時脈產生與解碼電路 12229pif.doc/008 26 200405152 拾、申請專利範圍： 1. 一種用來產生一時脈訊號以及解碼資料之裝置，其 係適用於一非接觸式積體電路裝置中，該用來產生一時脈 訊號以及解碼資料之裝置包括= 一接收器，用來接收具有一暫停週期的一射頻訊號； 一分頻器，用來分頻所接收到的該射頻訊號，以提供 一分頻訊號； 一第一計數器，用來計算在所接收到該射頻訊號的每 一非暫停週期上的該分頻訊號的一周期； 一第二計數器，用來計算該分頻訊號的一周期；以及 一解碼器，響應該第一及該第二計數器的複數個輸 出，產生一同步時脈訊號以及一解碼資料訊號。 2. 如申請專利範圍第1項所述之用來產生一時脈訊號 以及解碼資料之裝置，其中該第一計數器是在該射頻訊號 的該暫停週期期間所重置。 3. 如申請專利範圍第1項所述之用來產生一時脈訊號 以及解碼資料之裝置，其中該第二計數器是在該同步時脈 訊號的一下降邊緣所重置。 4. 如申請專利範圍第1項所述之用來產生一時脈訊號 以及解碼資料之裝置，其中該射頻訊號是根據一種ISO-14443 A 型介面標準。 5. 如申請專利範圍第4項所述之用來產生一時脈訊號 以及解碼資料之裝置，其中該解碼器更加包括響應該第一 及該第二計數器的該些輸出，產生用來指示一所接收到的 訊框結束的一訊號。 12229pif.doc/008 27Signal & RF_ IN Level RX IN_CNT4 STATE—CNT3 Hexa Code [3] [2] [1] [〇] [2] [i] [〇] RX_IN_CNT4 [3: 〇] || STATE_CNT3 [2: 〇] END_OF_R X 11111111 (2 ETU) 1 1 0 1 1 1 0 D6 1 1 1 1 0 0 1 FI 1 1 1 1 1 1 0 1 F5 When the logical combination of the counter 24o and the MO output is shown in Table 7, the clock generation and The decoding circuit 260 activates the frame end signal END_OF_RX to a high level. According to the above embodiments of the present invention, the clock generation and data recovery circuit 2000 will generate a synchronous clock signal ETU_RX_CLK with a frequency of 0.11 MHz, and decode the data signal rXj [N, making it suitable for receiving ISO / IEC 14443 A Type agreement information. 23 12229pif.doc / 008 200405152 When the data transmission rate is 106Kbps and 1-bit data appears during the 32 cycles of the clock signal, the pause period of the 1-bit data is 8 clock cycles. If the pause period falls within the range of 6 to 7 clock periods, the circuit 100 shown in FIG. 4 can recover an accurate signal. Under actual operating conditions, when the 6 ~ 11 clock cycle corresponds to 1.764 ~ 3.234ps, the pause period of the clock signal RF_CLK is 0.294 ~ 4.704ps. The clock generation and data restoration circuit 200 of the non-contact integrated circuit card has a counter 240 with a 4-bit counter and a counter 250 with a 3-bit counter to track the change of the pause period. The circuit 200 allows the pause period to be varied within a range of 0.884 to 4.129 μδ. For the data transmission rate of 212Kbps, the pause period can be changed in the range of 0.589 ~ 2.604ps, and for the data transmission rate of 424Kbps, the pause period can be allowed to be changed in the range of 0.294 ~ 0 · 884μδ . As mentioned above, a radio frequency signal received by a contactless integrated circuit card from a card reader generates a synchronous clock signal applicable to the ISO / IEC 1444 Type A protocol and decodes the received data signal . In addition, even when the pause period of the radio frequency signal is changed within a predetermined range, accurate decoding results can be obtained. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. Brief description of the drawings 12229pif.doc / 008 24 200405152 Figures 1A and 1B are schematic diagrams showing the communication signals of the 1S0 / IEC 14443 protocol type A and B interfaces. Figure 2 is a waveform diagram of a signal transmitted from a card reader to an integrated circuit card. Figures 3A and 3B are schematic diagrams showing the data frames of the ISO / IEC 14443 Type A protocol. Fig. 4 is a unit diagram showing a clock generation and data recovery circuit of a non-contact integrated circuit card according to the present invention. Fig. 5 is a timing chart showing the operation of various signals of the circuit shown in Fig. 4. Fig. 6 shows a preferred embodiment of the clock frequency divider shown in Fig. 4. FIG. 7 shows a clock generation and data recovery circuit of a non-contact integrated circuit card that can accurately recover codes even with a large number of task changes during a pause period, according to another embodiment of the present invention. Fig. 8 is a timing chart showing the operation of various signals of the circuit shown in Fig. 7. Description of graphical symbols: 100: clock generation and data recovery circuit 110: radio frequency unit 120: clock frequency divider 120a: input endpoint 120b: output endpoint 121 ~ 127: frequency divider 12229pif.doc / 008 200405152 128: Bit rate selector 130: OR gate 140: 3-bit counter 150: 2-bit counter 160: clock generator and decoder unit 170: reset controller 200: clock generation and data recovery circuit 210: radio frequency unit 220: Clock frequency divider 230: OR gate 240: 4-bit counter 250: 3-bit counter 2 60: Clock generation and decoding circuit 12229pif.doc / 008 26 200405152 Scope of patent application: 1. One type A device for generating a clock signal and decoding data is suitable for a non-contact integrated circuit device. The device for generating a clock signal and decoding data includes a receiver for receiving a pause period. A radio frequency signal; a frequency divider for dividing the received radio frequency signal to provide a frequency division signal; a first counter for calculating each non-pause cycle of the radio frequency signal received On the A period of the frequency-divided signal; a second counter for calculating a period of the frequency-divided signal; and a decoder in response to a plurality of outputs of the first and second counters to generate a synchronous clock signal and Decode data signals. 2. The device for generating a clock signal and decoding data as described in item 1 of the scope of the patent application, wherein the first counter is reset during the pause period of the radio frequency signal. 3. The device for generating a clock signal and decoding data as described in item 1 of the scope of the patent application, wherein the second counter is reset at a falling edge of the synchronous clock signal. 4. The device for generating a clock signal and decoding data as described in item 1 of the scope of patent application, wherein the radio frequency signal is based on an ISO-14443 A-type interface standard. 5. The device for generating a clock signal and decoding data as described in item 4 of the scope of patent application, wherein the decoder further includes responding to the outputs of the first and second counters to generate a signal for indicating a A signal at the end of the received frame. 12229pif.doc / 008 27