JP2003333112A - Demodulator - Google Patents

Abstract

(57) [Problem] To demodulate data from a received radio wave using ASK 100% modulation, a large-scale circuit such as a PLL is required so that a demodulation clock is not interrupted even during a pause period. A clock is not supplied during a pause period, but when a pause state is set, a counter number corresponding to the pause period is preset in a counter circuit. After the pause is released, re-counting is started from the preset value, so that the demodulated clock is not interrupted even if there is a pause period. This enables normal data demodulation.

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a demodulator.
More specifically, the present invention relates to an apparatus for demodulating a signal which is ASK 100% modulated. [0002] In recent years, non-contact IC cards have been used not only for telephone cards and tickets, but also for applications such as FA and physical distribution. Furthermore, it is becoming a situation that each person owns a plurality of non-contact IC cards. A non-contact IC card does not have a contact portion, so it is resistant to poor contact or dirt, and can simultaneously read a plurality of cards existing in a communication area. Because of these advantages, non-contact IC cards are expected to be used in a wide range of fields in the future. FIG. 12 is a conceptual diagram showing the connection between a non-contact IC card and a reader / writer. Reader / writer 801
Includes an antenna 803 for transmitting / receiving a data signal, a modulation circuit 807 for modulating data, a demodulation circuit 812 for demodulating data, a control circuit 805 for controlling modulated / demodulated data, and reading / writing of controlled data. And a memory 806 to be executed, and is connected to a controller or the like that inputs and outputs data. On the other hand, the non-contact IC card 802 includes an antenna 804 for converting a part of a magnetic field radiated as data from the reader / writer 801 into an electric signal on a predetermined substrate or film, and a modulation circuit 811 for modulating data.
, A demodulation circuit 808 for demodulating data, a control circuit 809 for controlling the modulated / demodulated data, and a memory 810 for reading / writing the controlled data. The reader / writer 801 having received a command signal such as a calling signal or a processing request signal from the controller accesses the memory 806 by the control circuit 805 and outputs the signal to the modulation circuit 8.
The control command signal is transmitted to the non-contact IC card 802 via the antenna 803. [0006] The modulated signal transmitted from reader / writer 801 is received by antenna 804 of non-contact IC card 802, the modulated signal is demodulated by demodulation circuit 808, and the demodulated signal is transmitted to control circuit 809 by a control command. Sent as a signal. The control command signal is executed by the memory 810 and transmitted to the modulation circuit 811 as a response signal, a result response signal, or the like, and the modulated signal is transmitted to the antenna 8.
04 to the reader / writer 801. [0007] A reader / writer 801 that receives a modulated signal transmitted from a non-contact IC card 802 by an antenna 803
Performs demodulation of the modulation signal in the demodulation circuit 812 and transmits the demodulated signal to the control circuit 805. The signal transmitted to the control circuit 805 accesses the memory 806,
Sent to controller. As described above, the reader / writer and the non-contact I
Data communication is performed with the C card. International standard ISO / IEC14443-
In Type 2, Type A and Type A are used as modulation and demodulation methods of data transmitted between the non-contact IC card and the reader / writer.
peB are defined. In Type A, ASK 100% modulation is specified as a modulation method of data transmitted from a reader / writer to a non-contact IC card. T
The non-contact IC card of type A demodulates ASK 100% modulated data from a reader / writer as follows. FIG. 13 shows an example of the configuration of a non-contact IC card that receives ASK 100% modulated data. A non-contact IC card transmits radio waves radiated from a reader / writer to an antenna 9.
01 is received. Antenna 901 and tuning capacity 90
2 constitutes a resonance circuit, and is set to a resonance frequency at which radio waves can be efficiently received. Antenna 90
The signal received at 1 is a power supply circuit 903, a detection circuit 904,
The clock is supplied to the clock circuit 905. The power supply circuit 903 rectifies the signal received by the antenna 901 to obtain a power supply for operating the non-contact IC card itself. Detection circuit 904
Then, an envelope detection is performed on the signal received by the antenna 901 to obtain an envelope detection output. The output of the envelope selection detection is supplied to the demodulation circuit 90.
6 and the data is extracted. Control circuit 907
Interprets the extracted data, executes read / write to the memory 909, and transmits the result to the reader / writer via the modulation circuit 908 and the antenna 901. Next, the international standard ISO / IEC14443
The ASK 100% modulation method specified in -2 will be described. In the ASK 100% modulation method, when there is no signal, FIG.
As shown in (1), a continuous 13.56 MHz unmodulated wave is supplied to the antenna. As shown in FIG. 15, the ASK 100% modulated wave has a period during which the 13.56 MHz radio wave is interrupted. The period during which radio waves are interrupted is called a pause. Data to be transmitted is represented by where the pause is inserted on the time axis. [0012] In ISO / IEC14443-2, Modified Miller modulation is adopted as a method of inserting a pause. The correspondence between the pause insertion position and the data in the Modified Miller modulation is called a coding rule, and is as shown in FIG. FIGS. 17 to 22 show specific bit patterns reflected on the received radio waves in accordance with the rules of FIG. 17 to 22, the bit period is the time allocated to 1-bit data transmission, and its value is 9.44 μS. The principle of demodulating the bit data from the envelope detection output generated from the received radio wave modulated by the Modified Miller modulation will be described with reference to FIG. In FIG. 23, as the clock cycle of the demodulation clock, a frequency that is の of the transmission bit cycle of the modulated data is selected. Further, it is assumed that the phase is determined so that the rising edge always occurs at the start point of the bit period. Under such conditions, first, the envelope detection output is frequency-divided at the falling edge to obtain a frequency-divided signal. The delayed signal is obtained by latching the frequency-divided signal at the rising edge of the demodulated clock. The delay signal is obtained by delaying the frequency-divided signal by one period of the demodulated clock. An exclusive OR of the frequency-divided signal and the delay signal is performed to obtain an EOR signal. EOR
When a signal is latched at the falling edge of the demodulated clock indicated by the arrow of the demodulated clock to obtain a sampling signal, the value of the sampling signal becomes demodulated data. This is Modified Miller
This is the principle of demodulation. The demodulated clock shown in FIG. 23 is generated by binarizing a received radio wave, which is an analog signal, and then performing frequency division. FIG. 24 shows waveforms of respective parts when the non-contact IC card of FIG. 13 receives an ASK 100% modulated wave. The clock circuit 905 binarizes the received radio wave and outputs a clock having the same frequency as the received radio wave. During the pause period during which the received radio wave is interrupted, the clock output from the clock circuit 905 also stops. A signal obtained by simply dividing the clock stops during the pause period in the same manner as the clock, and thus cannot be used as a demodulation clock for performing the Modified Miller demodulation shown in FIG. Non-contact I of FIG.
In the C card, a clock after interpolation is generated by the transmission circuit 908 and the PLL circuit 910 while maintaining the same frequency as the non-modulation period without stopping the pause period from the clock, and the divided clock is divided by the frequency divider circuit 908. Thus, a desired demodulated clock is obtained. It is important from the viewpoint of cost and reliability that a non-contact IC card is constituted by a one-chip LSI.
Mounting a circuit increases the circuit size and the price. In general, in the non-contact IC card, the operating power is also obtained from the received radio wave, but the communication data from the reader / writer to the non-contact IC card includes ASK 100%.
When a modulated wave is used, there is a pause period during which the received radio wave is interrupted, and during this period, the power supply to the non-contact IC card is also interrupted. In a conventional non-contact IC card, it is necessary to incorporate a large-capacity capacitor in order to operate a LSI by supplying a demodulation clock by a PLL circuit even during a power supply interruption period. Further, even if a large-capacity capacitor is incorporated, the communication distance is sacrificed because the power supply by radio waves is reduced. The present invention has been made to solve the above problems, and an object of the present invention is to provide a demodulator capable of reducing the circuit scale. [0018] A demodulation device according to the present invention includes a clock circuit, a detection circuit, a counter circuit, and a demodulation circuit. The clock circuit binarizes the ASK 100% modulated signal to generate a clock. The detection circuit performs envelope detection on the ASK 100% modulated signal. The counter circuit is preset according to the output state of the detection circuit and counts the clock from the clock circuit. The demodulation circuit samples the output of the detection circuit based on the change point of the output of the counter circuit. Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated. <Overall Configuration of Non-Contact IC Card> FIG.
FIG. 1 is a block diagram showing an entire configuration of a non-contact IC card according to an embodiment of the present invention. The contactless IC card shown in FIG. 1 includes an antenna 101, a tuning capacitor 102, a power supply circuit 103, a detection circuit 104, a clock circuit 105,
Counter circuit 110, demodulation circuit 106, control circuit 1
07, a memory 109, and a modulation circuit 108. The antenna 101 receives radio waves radiated from a reader / writer (not shown). Tuning capacity 102
Constitutes a resonance circuit with the antenna 101 in order to receive radio waves efficiently. The power supply circuit 103 includes an antenna 101
Rectifies the received signal to generate a power supply for operating the contactless IC card itself. The detection circuit 104 performs envelope detection on the signal received by the antenna 101 to obtain an envelope detection output. The clock circuit 105 binarizes a signal received by the antenna 101 to generate a clock. The counter circuit 110 counts the clock from the clock circuit 105, resets the count value each time the count value reaches a predetermined value (division number), and resets the count value to one of the division number.
/ 2, the output level (H level, L level) is switched. The output of the counter circuit 110 is supplied to the demodulation circuit 106 as a demodulation clock. The counter circuit 110 presets a count value according to the state of the envelope detection output from the detection circuit 104. Demodulation circuit 10
6 samples the envelope detection output from the detection circuit 104 based on the change point of the demodulation clock from the counter circuit 110, and extracts demodulated data from the envelope detection output. The control circuit 107 interprets the demodulated data and
9 is read / written and the result is
Give 8 The memory 109 is a memory for reading / writing data. The modulation circuit 108 modulates the data supplied from the control circuit 107 and modulates the antenna 1
Give to 01. <Generation of Demodulated Clock> Next, a counter circuit 110 is generated from the clock generated by the clock circuit 105.
The operation of generating a demodulated clock will be described. FIG. 2 is a circuit diagram of the counter circuit 110, and FIG. The counter circuit 110 counts the clock and generates a demodulated clock. As shown in FIG. 3, while the envelope detection output is at the L level, that is, A
It is preset to a certain value during the SK 100% modulation period.
When the envelope detection output becomes H level, the counter circuit 110
Restarts counting. FIGS. 4 to 6 illustrate an operation of generating a demodulated clock from a clock having a pause. The frequency division ratio of the clock circuit 110 is determined so as to generate a demodulated clock that is の of the bit period of the modulated data from the clock. This is to match the cycle of the demodulated clock and the modulated data described in the Modified Miller demodulation principle of FIG. Specifically, the modulation data speed is 10
Since it is 6 Kbps, the demodulation clock is 13.56 MHZ.
The frequency is 212 KHz obtained by dividing the frequency of the z clock by 64, and the timing chart of FIG. The preset value is such that the envelope detection output is L
The value is set to be larger than the value counted when it is assumed that the clocks are continuous during the level period. By doing so, as shown in FIGS. 5 and 6, the duty of the demodulated clock fluctuates, but the demodulated clock is always resynchronized for each pause of the envelope detection output. The number of demodulated clocks per one cycle of the detection output is the same as that of the conventional example shown in FIG. <Demodulation of Bit Data> Next, an operation of demodulating bit data from an envelope detection output generated from a received radio wave modulated by Modified Miller modulation will be described with reference to FIG. The envelope detection output is frequency-divided at the falling edge to obtain a frequency-divided signal. The delayed signal is obtained by latching the frequency-divided signal at the rising edge of the demodulated clock. An exclusive OR of the frequency-divided signal and the delay signal is performed to obtain an EOR signal. When the sampling signal is obtained by latching the EOR signal at the falling edge indicated by the arrow of the demodulation clock, the value of the sampling signal becomes demodulated data. Further, since the clock is stopped during the pause period, the power consumed by the circuit is very small. <Relationship Between Preset Value and Pause Period> Next, the relationship between the preset value of the counter circuit 110 and the pause period of the envelope detection output will be described. Referring to FIG. 8, in this embodiment, it is assumed that the time of one bit section of the envelope detection output is 1 / communication frequency = 1 / 105937.5 ≒ 9.44 μs. This is a frequency obtained by dividing the frequency of the unmodulated wave of 13.56 MHz by 128. In addition, 105937.5
Is the communication speed of 106 kbps and the decimal point of Hz.
It is a value that displays the frequency up to the digit. The frequency of the demodulated clock is 21187
At 5 Hz, the average frequency is twice the communication frequency. This is a frequency obtained by dividing the unmodulated wave by 64, and the counter circuit 110 in FIG.
The frequency is divided by 4. The following three conditions are required for the demodulated clock. [Condition 1] Two periods exist in one bit section. [Condition 2] The duty may vary. [Condition 3] The phase at which the demodulated clock is at the H level when the envelope detection output is at the L level. From condition 3 and FIG. 4, the counter preset value must be 32 or more and 63 or less. Outside this range, the demodulated clock is at L level while the envelope detection output is at L level. Here, the pause period is 0.5 μs to 4.0 μs.
It fluctuates up to 5 μs. When the pause period is the minimum (0.5 μs), as shown in FIG. 9, if the preset value is between 32 and 63, the conditions 1, 2, and 3 required for the demodulation clock are satisfied. On the other hand, when the pause period is the maximum (4.5 μs), as shown in FIG.
In this case, the condition 1 required for the demodulated clock is not satisfied. When the preset value is 63, the condition is satisfied. Thus, the preset value that satisfies the condition changes according to the pause period. Next, the relationship between the preset value and the pause period will be generalized and described. As shown in FIG. 11, one bit section = T, pause period = t1, period from the end of the pause period until the demodulated clock goes to L level = t2, and one of the demodulated clocks from the end of the pause period. Period from the time when the cycle has elapsed to the start of the next bit section = t3,
It is assumed that the preset value = N. Then, t2 = demodulation frequency cycle × (count number from preset value to one cycle) プ リ セ ッ ト one cycle count number = (T ÷ 2) ×
(64−N) ÷ 64, t3 = T−t1−t2− (T ÷ 2) = (T ÷ 128) × N−t1... In the formula A, (T ÷ 2)>t3> 0 is a condition to be obtained. If t3 ≦ 0, the cycle of the demodulated clock is insufficient, and if t3 ≧ (T ÷ 2), the cycle of the demodulated clock is excessive. From the condition of t3> 0, (T な る 128) × N−t1> 0 and N> t1 ÷ (T ÷ 128). Here, T = 9.44 μs, t1 = 4.5 μs
Is obtained, N> 61 is obtained. Therefore, the preset value N is 62, 63
Only two types. Consider the magnitude relationship between (T ÷ 2) and t3. (T ÷ 2) -t3 = (1 ÷ 4-N ÷ 128) × T-t1... B The formula B is minimum at N = 63 and t1 = 0.5 μs, and (1 ÷ 2−63 ÷ 128) × 9.44−0.5 ≒ 0.57, so that (T ÷ 2)> t3 The conditions are also satisfied. Therefore, the preset value N may be either 62 or 63. <Effects> As described above, according to the present embodiment, a large-scale circuit such as a PLL circuit is not required, and the clock is stopped during the pause period of the ASK 100% modulated wave, so that the power during the pause period is reduced. ASK1 does not require a large-capacity built-in capacitor because of low consumption.
It is possible to demodulate data from a 00% modulated wave. Although an example in which the present invention is applied to a non-contact IC card has been described, the present invention can be similarly applied to a non-contact IC tag and the like. According to the demodulation device of the present invention, the ASK10
Data can be demodulated from a 0% -modulated signal by a small-scale circuit with low power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an overall configuration of a non-contact IC card according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a counter circuit shown in FIG. FIG. 3 is a diagram for explaining an operation of the counter circuit shown in FIG. 2; FIG. 4 is a timing chart for explaining an operation of the counter circuit shown in FIG. 2; FIG. 5 is a timing chart for explaining a frequency dividing operation by the counter circuit shown in FIG. 2; FIG. 6 is a timing chart for explaining a frequency dividing operation by the counter circuit shown in FIG. 2; FIG. 7 is a timing chart for explaining an operation of demodulating bit data from an envelope detection output. FIG. 8 is a timing chart for explaining a relationship between a preset value of a counter circuit and a pause period. FIG. 9 is a timing chart for explaining a relationship between a preset value of a counter circuit and a pause period. FIG. 10 is a timing chart for explaining a relationship between a preset value of a counter circuit and a pause period. FIG. 11 is a timing chart for explaining a relationship between a preset value of a counter circuit and a pause period. FIG. 12 is a block diagram showing a connection between a non-contact IC card and a reader / writer. FIG. 13 is a block diagram illustrating a configuration of a conventional non-contact IC card that receives ASK 100% modulated data. FIG. 14 is a diagram showing a signal waveform when no modulation is performed in the ASK 100% modulation method. FIG. 15 is a diagram showing a signal waveform modulated by ASK 100%. FIG. 16 is a diagram illustrating a coding rule in Modified Miller modulation. FIG. 17 is a diagram illustrating a bit pattern in Modified Miller modulation. FIG. 18 is a diagram illustrating a bit pattern in Modified Miller modulation. FIG. 19 is a diagram illustrating a bit pattern in Modified Miller modulation. FIG. 20 is a diagram illustrating a bit pattern in Modified Miller modulation. FIG. 21 is a diagram illustrating a bit pattern in Modified Miller modulation. FIG. 22 is a diagram illustrating a bit pattern in Modified Miller modulation. FIG. 23 is a diagram illustrating the principle of Modified Miller demodulation. FIG. 24 is a diagram showing waveforms of respective units when an ASK 100% modulated signal is received. [Description of Signs] 101 antenna, 102 tuning capacitance, 103 power supply circuit, 104 detection circuit, 105 clock circuit, 106
Demodulation circuit, 107 control circuit, 108 transmission circuit, 1
09 memory, 110 counter circuit.

Claims (1)

Claims: 1. A clock circuit for generating a clock by binarizing an ASK 100% modulated signal, an envelope detecting circuit for detecting the ASK 100% modulated signal, and a detecting circuit A demodulator characterized by comprising: a counter circuit preset according to an output state and counting a clock from the clock circuit; and a demodulation circuit sampling an output of the detection circuit based on a change point of an output of the counter circuit. apparatus.