SU944123A1 - Device for measuring error coefficient - Google Patents

Description

(54) DEVICE FOR MEASUREMENT OF COEFFICIENT

ERROR

one . . .

The invention relates to measuring technology, in particular, to measuring the reliability of information transfer, and can be used to assess the quality of transmission of discrete information in a wide linear paths of electrical communication systems.

A device for measuring the error rate is known, containing successively connected a corrector on a side, a shift register and a comparator, the second input of which is combined by the first input of the error corrector, the common signal of the test signal, the first counter and the serially connected key and ($ second counter C 1

However, in the known device there is the possibility of a false sync. since if, after filling the first counter in the shift register, 20 20 tons of error information were found, it would distort at least one bit of input information, which in turn will generate new errors, and this process continues until until the second counter is filled up, which eventually logs the errors that are missing in the linear signal.

The purpose of the invention is to improve the measurement accuracy by eliminating false synchronization.

To do this, the device for measuring the error rate, containing successively connected error corrector, shift register and comparator, the second input of which is combined with the first input to | The error rector, the test signal input, the first counter and the serially connected second and second counters, the first, second and third tfiggers, the coincidence unit and the decoder are entered, the output of the first counter is connected to the input of the decoder, the first, second and third outputs of which connected respectively to the first input of the coincidence unit and to the zero inputs of the first and second triggers, the output of the coincidence unit is connected to the single inputs of the first and second triggers, the installation inputs of which are combined with The first input of the counter is the input of the initial setup, and the output of the comparator is connected to the single input of the third flip-flop, a triple input and the direct and inverse outputs of which are connected respectively to the second flush-trigger output, to the second error-correction input and to the combined second the input of the coincidence unit and the first input of the key, the second input of which is connected to the direct output of the trigger, the inverse output of which is connected to the second input of the first counter and the third input of the coincidence block. The drawing shows a structural electrical circuit of the proposed device TVD. The device contains a register 1 shift comparator 2, an error corrector 3, a key two counters 5 and 6, three triggers 7, 8 9, a coincidence unit 1O, and a decoder 11 The device operates as follows. All the work on the fulfillment of the functions assigned to it is divided into three stages: the installation of the initial state; recording information and checking for false synchronization. At the first stage, the signal of the initial setup and, arriving at the installation inputs of the counter 5 of the trigger 7 and 8, sets the output of the counter 5 and the direct outputs of the trigger 7 and 8 to the logical // -I // state. At the first and second outputs of the decoder 11 the logical level O is set, and the third is logical 1, and the signals from the outputs of the triggers 7 and 8 close the trigger 9, and the key 4 and the information from the output of the comparator 2 will not flow to the inputs of the corrector 3 and the counter 6. After the installation pulse completes the second stage of the work, during which time It writes the input information through the equalizer 3, which performs the logical function OR, to the shift register 1. At the same time, the counter 5 begins to work, at the output of which the first pulse appears after N clock intervals. The number K1 is chosen from the ratio S 7 I, where i is the length of the register 1 shift. Thus, when counter 5 reaches the counting ratio, the shift register 1 becomes filled with input information. At the moment of the end of the second stage, the following changes occur in the circuit: at the first output of the decoder 11 a logic level is set; this signal arrives at the R input of the trigger 8, sets the output level of the logic trigger 9 at its output to Pass the information from the comparator 2 output to the equalizer 3 input (since the logic level 0 is set at the input of the trigger 9), and the corrector 3 begins to perform the logical function EXCLUSIVE OR; the key 4 is not still closed by the signal from the output of the trigger 7, therefore the error pulses produced by the comparator are not received at the input of counter 6 (the counter of errors). After the input of the counter N of the N-th clock pulse, the third stage of the operation of the device begins - checking the synchronization accuracy. At this stage, the third output of the decoder 11 is set to a logic level O, the open unit 1O. Therefore, if during the synchronization test stage, at least one error pulse occurs at the output of the comparator 2, it goes through trigger 9 and block IO to the set inputs of flip-flops 7 and 8, and from the output of trigger 7 it goes to the installation inputs of counter 5, returning all circuit to the state corresponding to the beginning of the second stage. If, during the third stage, no error is received at block 1O, the second output of the decoder 11 sets the logic level 1, which sets the level of logical O at the output of the trigger 7 and opens the key 4. From this moment the error pulses from the output of the comparator 2 through the trigger 9 and the key 4 begin to arrive at the input of the counter 6, and the device for measuring the error rate starts to function normally. Thus, introducing into the known nepfeoro device, the second and third triggers, the coincidence block and the decoder allows determining the fact of false device synchronization and prohibiting the device operation for the time required for re-synchronization. The time spent on checking and (if necessary) resynchronizing the device is 3N clock intervals. The maximum length of the shift registers used in generators to check the qi} paths is 23, i.e. the additional time required is only 70 - 8 o clock intervals, while the law of error distribution in the path is not distorted, which allows their further statistical processing. The formula for measuring the error rate, containing a serially connected error corrector, a shift register and a comparator, the second input of which is combined with the first input of the error corrector, which is the input of the test signal, the first counter and. hence the connected key and second counter, characterized in that; that, in order to improve measurement accuracy by eliminating the effect of spurious synchronization of the device, the first, second and third triggers, a matched NIN unit and a decoder were introduced, the output of the first counter connected to the input of the decoder, the first, second and third outputs

BCS

The CUIHO / IO 9 23 of which is connected respectively to the first input of the coincidence unit and to the zero inputs of the first and second flip-flops, the output of the coincidence block is connected to the single inputs of the first and second flip-flops, the installation inputs of which are combined with the first input of the first counter installation, and the comparator output is connected to a single input of the third trigger, zero input and the direct and inverse outputs of which are connected respectively with the output of the second trigger, to the second input of the error corrector and combining the second input of the coincidence and the first input key, a second input coupled to a direct output of the first flip-flop inverse output is connected to the second input yervogo counter and a third input block matcher. Sources of information taken into account in the examination 1. UK patent number 1431218, cl. H 4 R, 1976 (prototype).

Claims (1)

'Claim A device for measuring the error coefficient, comprising a series-connected error corrector, a shift register 15 and a comparator, the second input of which is combined with the first input of the error corrector, which is the input of the test signal, a first counter and a series-connected key and a second 20 counter, characterized in; in order to improve the accuracy of measurements by eliminating the influence of false synchronization of the device, the first, second and third triggers, a coincidence unit and a decoder are introduced, while the output of the first counter is connected to the input of the decoder, the first, second and third outputs of which are connected respectively with the first input of the coincidence unit and with zero inputs of the first and second triggers, the output of the coincidence unit is connected to the unit inputs of the first and second triggers, the installation inputs of which are combined with the first input of the first counter are the input of the initial setup signal, and the comparator output is connected to the single input of the third trigger, the zero input and the direct and inverse outputs of which are connected respectively to the output of the second trigger, to the second input of the error corrector, and to the combined second input of the coincidence unit and the first input key, the second input of which is connected to the direct output of the first trigger, the inverse output of which is connected to the second input of the first counter and to the third input of the coincidence unit.