SU922734A1 - Device for computing sine and cosine functions - Google Patents

Description

the higher bits of the argument, the output of the first intermediate register is connected to the input of the second intermediate register connected via the third memory block to the input of the third intermediate register, output connected to the input of the fourth intermediate register, the output of which is connected to the first input of the first adder, the second input of which The second intermediate register is connected to the output of the shifter, the first input of which is connected to the output of the sixth intermediate register connected via the fourth memory block to the output the seventh intermediate register, the input of which is connected to the output of the second adder, the second input of the shifter is connected to the output of the eighth intermediate register, the input of which is connected to the output of the decoder, the input of which is connected to the output of the seventh intermediate register, the output of the second memory block is connected to the input of the ninth intermediate register, the output of which is connected to the first input of the second adder, the second input of which is connected to the output of the ten intermediate register, whose input is connected to the output of the first block The memory, the control inputs of the high and low bits are connected to the first clock input of the device, the control inputs of the first, ninth and tenth intermediate registers are connected to the second clock input of the device, the control inputs of the second and seventh intermediate registers are connected to the third clock input of the device, the control inputs of the third, sixth and eighth intermediate registers are connected to the fourth clock input of the device, the fifth clock input of which is connected to the control inputs of the fourth The first and fifth intermediate registers, the control input of the output register is connected to the sixth clock input of the device.

The drawing shows the block diagram of the device.

The device contains a register of 1 high bits of the argument, a register of 2 lower bits of an argument, intermediate registers 3–12, blocks 13 16 of fixed memory, adders 17 and 18, a decoder 19, a shifter 20, an output register 21, clock inputs 22–27 devices.

Clock pulses arriving at device registers are generated in a clock pulse generator (not shown). Changing the contents of the registers occurs on the leading edge of each write pulse. To eliminate races, the pulses are shifted with the help of delay elements in each

steps up to time t. The breakdown of the device by registers allows all steps to operate independently, so immediately after the release of the first step, a new operand is loaded into it, and in the second step, the operand that has passed the first step is already processed, and so on. The sequence of operations performed on operands during the passage of all stages determines the operation of calculating the sine or cosine. The performance of conveyor devices under the condition of processing arrays in which the number of operands is substantially greater than the number of stages of the conveyor is characterized by the duration of the data advance cycle T along the conveyor. The duration of tact T is determined by the maximum propagation delay of the NIN signal that combinational circuits of a certain stage of the conveyor have, in this case steps containing the adder.

Memory block 13 is designed to store a table of 2dX cos X values in the case of calculating a sine function and a table of tog sin Xg values in the case of a cosine function, memory block 14 provides this personal conversion of dx to Water L x; memory block 15 stores a table of sin Xg values in case of calculating sine and cos XQ in case of cosine calculation, memory block 16 performs transformation of the form Z - 2.

 Intermediate registers 3-12 are designed to store the results of intermediate calculations and to provide a pipelined processing method.

The device performs calculations based on the table-algorithmic method. The value of the sine and cosine functions is sufficient to find within the range of the argument from O to, since the values of these functions for an arbitrary value of the argument, because of their periodicity, can be obtained from the values of functions in the interval 0, by an additional operation such as addition or change of sign.

. The calculation of the functions sin x cos x. From the argument y. {0 x. ) is produced in the device based on the following relationships.

Claims (2)

Let x0 be the number formed by the higher bits of the argument, A x the number formed by the lower bits of the argument. That is, we divide the argument, x, Xg, .... Xp by the sum of the nodal point, x is ,, X | j,. . .X ,, and increment lx x - x. Then for the sine days, we have the relation 4sin X sin (Xo + dx) - sin xo 2 sin - 2cos (xo + and for the cosine function the ratio UCOS X cos (x (J + ix) - cos X 5 -2 sin-2 sin (X (5+): - dx. Sin performed with an error of E 2 which can be made beyond the limits of the discharge grid by appropriate choice of the parameter k. To calculate the cosine sine values, we get the expressions 5Jn) (sSiTiXQ + uSin% sSinX + l, eo ({un + eo (55 tosKo),. and ult + eoif Sinx) COSX COSXQ-fiCOSX COS) 2 Y where the parameter k must satisfy condition k. The device works as follows. The XQ value is stored in the high-order register of argument 1 , dx value - In the register of the lower order of the argument series 2. In the first operation cycle of the device in memory block 13, the value XQ received from register 1 ,, forms the value Sogij cos XQ when calculating the sine and 2. sin XQ when calculating the cosine. the value dx forms the value gogij ax. In the second cycle, these values are written to intermediate registers 4 and 5, respectively, and the value x from register 1 is written to intermediate register 3. On the adder 17, an expression equal to the sum of the contents of registers 4 and 5 is formed. The second in the third cycle is recorded in the prog} daily register 7, and in Intermediate register 6, the value of register 3 is written. From the value X coming from register b, in memory block 15, the value sin is formed when calculating the sine and cos x Q when calculating the cosine, and according to the contents of register 7 in the block 16 constant memory forms the value j (.eoqfiui (4i ° osXo), when calculating the sine and the value (8os {, dx + eo1 {5dt, Wo)) is the inverse code when calculating the cosine, i.e., in block 16, the transformation z 2 Since a characteristic appears during the potentiation, a decoder 19 is inserted in the devices, which, obsessed register 7 generates a code that indicates how much it is necessary to shift the value from the output of block 16 to take into account the characteristic. In the fourth clock cycle, the contents of blocks 15 and 16 and the decoder 1 $ are written, respectively, into intermediate registers 8-10. The specified shift, and from its output, the resulting value is written in the fifth clock cycle to the intermediate register 12, and the register 11 is written to the register 11. The sum of the intermediate register 11 and the content of the intermediate register are summed on the accumulator 18. register 12, i.e., the result of the calculation is generated, which is written to the output register in the sixth clock cycle. The total amount of constant memory for sine and cosine is determined by the expression Q 4n-2n + 64-S) (3 (nk + l) + g), where S. Kogij k; r eogi Cn-k + l). Using this expression, it is possible by appropriate choice of the parameter k to obtain a device that provides the required accuracy of calculations with the minimum total amount of permanent memory. For we have Q 329 k. The device works on the conveyor principle. In each cycle, a new operand can be entered into it. After the first six clock cycles at the output of the device, we get the first result, and then with each tactical output of the device a new result appears, i.e. the device speed is determined by the duration of the cycle. The duration, on the other hand, in the proposed device is determined by the delay in the most time capacitive node, which is the adder, therefore the speed of the known device does not exceed T / 1 2tQbi6 2t (4 ,, + tc .. Since usually t 5, (,: 5 try and LIKE the speed of the proposed device is higher than the known V. 5 (times). Invention A device for calculating sine and cosine functions, containing registers of the highest and lowest bits of the argument, four memory blocks, an adder, a shifter, a decoder, output register, and the output register the higher-order bits of the argument are connected to the output of the first memory block, the output of the adder is connected to the input of the output register, which is different from the fact that, in order to improve speed, the device contains ten intermediate registers and a second c1 1mator, and the input of the first intermediate register connected to the output of the register of the higher bits of the argument, the output of the first intermediate register is connected to the input of the second intermediate register connected via the third memory block to the input of the third intermediate register, output Fourth intermediate register, whose input is connected to the first input of the first adder, the second input of which is connected through the fifth intermediate register to the output of the shifter, the first input of which is connected to the output of the sixth intermediate register connected via the fourth memory block to the output of the seventh intermediate the register, whose input is connected to the output of the second adder, the second input of the shifter is connected to the output of the eighth intermediate register, the input of which is connected to the output of the decoder, in One of which is connected to the output of the seventh intermediate register, the output of the second memory block is connected to the ninth intermediate register, the output of which is connected to the first input of the second adder, the second input of which is connected to the output of the tenth intermediate register whose input is connected to the output of the first memory block those controlling the inputs of higher registers and low-order bits are connected to the first so-called device input, the control inputs of the first, ninth and tenth intermediate registers are connected to the second clock input the control inputs of the second and seventh intermediate registers are connected to the third clock input of the device, the control inputs of the third, sixth and eighth intermediate the registers are connected to the fourth clock input of the device, the fifth clock input of which is connected to the control inputs of the fourth and fifth intermediate registers, the control input of the output register is connected to the sixth clock input of the device. Sources of information taken into account in the examination 1. USSR Author's Certificate No. 591857, cl. About R 7/38, 1978. 2. Potapov V.I., Nesteruk V.R., Florensov A.N. High-speed arithmetic logic devices. Computer, Novosibirsk, 1978, p. 29 - .32 (prototype).