SU542994A1 - Parallel action accumulator - Google Patents

Description

one

The invention relates to computing and can be used to build digital computer processors.

A known adder containing in each bit a trigger whose input is connected to the exit of the first OR element connected by the first input to the output of the first element AND, and the second input to the output of the second element AND, the first input of which is connected to the first input of the third element AND , to the second input of which is connected the direct output of the trigger, the inverse output of which is connected to the first input of the fourth element AND, the output of which is connected to the first input of the second element OR, connected by the second input to the output of the third element AND, and the output ohm - to the first input of the third element I of the neighboring most significant bit, the input bus is connected to the second inputs of the first and fourth elements I, and the control inputs of the device are connected to the second inputs of the first and second elements 1, 2. However, the known adder has a low speed, since the summation is carried out in two cycles, in the first of which the term is entered into the triggers and the formation of transfer signals, and in the second cycle the state of the triggers is repeated in accordance with the data in the first cycle transfer signals. It is also known a device that implements the idea of accelerating the transfer of a transfer signal by using bypass prices and containing five terms of the registers, a result register, a combination part for generating sum and transfer signals, as well as blocks for speeding up the passage of signals through a group of transfer bits 3. This adder

0 has a large amount of equipment and low speed, since the time of the addition in the mode of multiple summation is equal to twice the trigger flip time and the signal delay time in the combinational part. The closest technical solution to the invention is the cumulative parallel action adder, containing in each discharge the first trigger, the output of which is connected to the first input of the block

0 analysis, the first output of which is connected to the zero input of the first trigger, the second trigger, the output of which is connected to the second input of the analysis block, the third input of the analysis block of each bit is connected to the second output of the analysis block of the previous bit 4. It is also characterized by low speed how much time is spent on the propagation of the transfer signal in a sequential chain of analysis blocks.

The aim of the invention is to increase speed. In the simulated adder, this is achieved by introducing AND elements, inverters and inhibiting elements, such as the inputs of the first element I are connected to the two inputs of the locked element, which are connected respectively to the first and second inputs of the analysis unit, the output of the nerve element I connected with the first inputs of the second n of the third element I and through the inverter with the first input of the fourth element I, the second input of which is connected to the control bus and to the second input of the third element I, the output of which is connected to the first input About And, the second input of which is connected to the output of the inhibit element, and the output is connected to a single trigger input, the output of the fourth element And is connected to the fourth input of the analysis unit, the third input of which is connected to the third input of the element And is locked connected to the second output of the analysis unit, the inputs of the first elements And adjacent bits through the sixth elements And connected to the first input of the seventh element And, the second input of which is connected to the second input of the second element And the younger of quiet bits, and the output to the output bus, the inputs of the sixth elements And adjacent bits are connected through the eighth element And to the first input of the ninth element And, the second input of which is connected to the second input of the second element And the youngest of these bits, and the output - to the output bus.

The drawing shows the circuit of the described adder.

It contains in each bit the first triggers 1, the second triggers 2, analysis blocks 3, the first, second, third, fourth and fifth elements AND 4, 5, 6, 7 and 8, inverters 9, prohibition elements 10; control bus 11, input bus 12 and output bus 13, sixth, seventh, eighth and ninth elements AND 14, 15, 16 and 17.

The first term is in the first triggers 1, the second is in the second triggers 2, the transfer is formed by analysis blocks 3. Elements 4 produce a signal at the output if the states of both triggers 1 and 2 of this bit are not "zero". If triggers 1 and 2 of two or three adjacent bits are in a similar state, then a control signal is generated at the outputs of the corresponding And 4 elements. Depending on the number codes contained in Triggers 1 and 2, And 4 elements allow the signal The input cable 12 passes to the output busbar 13 along the shortest path. If in any bit the triggers 1 and 2 are in the state "1 and at the input of the analysis block 3 of this bit there is a transfer signal from the previous bit, then the signal from the output of the prohibit element 10 closes the fifth element And 8, prohibiting the reset trigger 1 in “O. If both triggers 1 and 2 are in any state in the state "O", the fourth element I 7 is opened through the inverter 9, and the addition pulse arrives from the control bus 11 to the input of the corresponding analysis unit 3. The dead-end accumulator action has a higher speed, compared with the known cumulative adders, in which the summation is carried out in two cycles, while in the described adder - in one cycle.

Claims (4)

1.Papernov A.A. Logical bases of digital computing technology. M., Soviet radio, 1972, p. 159, fig. 14. 2.Kartsev M.A. Arithmetic of digital machines, M., Science, 1969, p. 249, fig. 2-45. 3. Lehman, M. and Vourla N. Acceleration of the propagation of the transfer signal in binary arithmetic devices through the use of bypass circuits. Express information "Computer Engineering, No. 19, 1962, p." 1-13. 4. Khetagurov Ya.A. and others. Fundamentals of engineering design of control computers. Soviet radio, M., 1972, p. 104, fig. 4-17.