SU896621A1 - Microprogramme-control device - Google Patents

Description

one

The invention relates to digital computing and can be used as a microprogrammed computer control device.

A firmware control device containing memory blocks for storing addresses of microinstructions and their operational parts, address and buffer registers, a register of logical conditions., Decoders, address counters and microinstructions, AND elements, NOT, support elements and a clock pulse generator G are known is low efficiency due to the redundancy of the third storage unit, where the operating are recorded - parts of all microprogram microcommands.

The closest to the proposed technical essence and the achieved positive effect is a firmware control device containing a register of logical conditions, the output of which is connected to the first input of the first block of elements And, the output of which is connected to the input of logical conditions of the buffer register, the output of which is connected to the first input of the second a block of elements and whose output is connected to the information input of the first address register, the input of the operation code of which is the input of the operation code of the device, the output of the first register of the address is connected to the information input of the first decoder, the output of which is connected to the input of the first storage unit, the first address

10 the output of the first storage unit is connected to the direct input of the buffer register, the second address output with the input of the encoder, the output of logical conditions with the information input of the register of logical conditions, and the reset output with the input of setting the first address register to zero, the second input of the first block of AND elements connected with the input of the logical conditions of the device, the second input of the second block of elements And is connected to the output of the first element And, the first input of which through the first and second delay elements is connected to the first

25 output of the clock pulse pulse QQB, the second input of the first element And is connected to the output of the third element And, to the first input of the fourth element And, and through the first element

30 NOT with the first input of the second element

And, the second input of which is connected to the first input of the clock generator, the output of the second element I is connected to the input of setting the second address register to zero and the start input of the second decoder, the group of inputs of the third element I is connected to the group of outputs of the microinstruction counter, the first input of which is connected to the first output of the encoder, the second output of which is connected to the information input of the address counter, the input of the zero setting of which is connected to the inputs of setting the zero of the register of logical conditions, the buffer register, the start of the first decoder and the output of the fourth element I, and the output of the address counter to the information input of the second decoder, the output of which is connected to the input of the second storage unit, the output of which is connected to the information input of the second address register, the first bit output of which is connected to the third information input decoder, start input. Which is connected to the output of the first delay element, and the output of the third decoder is connected to the input of the third storage unit, the first output of which is Inonii with counting input address counter and a second counter input microinstructions February 1.

The disadvantage of this device is its low efficiency, due to the large redundancy of the third storage unit.

The purpose of the invention is to increase the efficiency of the firmware control device.

This goal is achieved by the fact that the device additionally contains a pulse counter, a shift register, an NAND element and a third block of AND elements, the information input of the pulse counter is connected to the second bit output of the address register, the counting input of the pulse counter And the first input of the sixth element And, the first input of the fifth element And is connected to the unit output of the control trigger, and the second input to the second output of the clock generator, the unit input of the control trigger is connected to the output the house of the second delay element, and the zero input through the second element is NOT connected to the second input of the sixth AND element and the output of the NAND element, whose input group is connected to the output group of the pulse counter, the output of the sixth AND element, is connected to the first input of the shift register, the second the input of which is connected to the output of the first delay element is the third, the input to the first output of the third storage unit, and the output to the first input of the third

the block of elements And, the second input of which is connected to the zero output of the control trigger, the output of the third block of elements And is the output of the device.

The proposed device provides an increase in efficiency by recording only the basic operating micro-instructions in the third storage block and forming the full set of operating micro-operations by cyclically shifting the corresponding basic operating micro-instructions by a specified number of bits.

The drawing shows a functional diagram of the firmware control device.

The device contains the first register 1 address, the first decoder 2, the first storage unit 3, the register 4 logical conditions, the first block 5 elements And, the buffer register 6, the second block 7 elements And, the encoder 8, the counter 9 microinstruction, the third element And 10, the first element 11, first delay element 12, second delay element 13, fourth element 14, trigger control 15, fifth element 16, pulse counter 17, AND-NE 18, sixth element 19, shift register 20, third block 21 elements And, the second element is NOT 22, generator of 23 clock pulses, first element Ent H 24, the second element And 25, the address counter 26, the second decoder 27, the second storage unit 28, the second address register 29, the third decoder 30, the third. storage unit 31, the operation code input 32, the input 33 of logical conditions, the device output 34 .

Reading the operating microcommand from the output of the firmware control device is carried out in two cycles.

The first cycle starts by reading information from the first storage unit 3: output of the address code of the first Microcommand of the next microcommand, address code of the first microcommand of the current sequence, code of verified logical conditions. The first cycle of operation ends by reading the information from the third storage unit 31 from the first output of the base operating microcommand.

After reading the address of the first microcommand of the current sequence, microcode 9 counts the code of the number of microcommands included in the sequence. During the operation of the firmware control device, the zero state of the micro-command counter 9 is an indication that the current micro-command sequence has been completed.

The contents of the micro-command counter 9 are changed in the process of implementing the sequence by decreasing by one the signals from the second output of the third storage unit 31 each time after reading the base operating micro-command from it. Reading the base operating microcommands from the third storage unit 31 is performed with low-frequency clock pulses from the first output of the generator 23 clock pulses. The address counter 26 is intended to form addresses of the next mic commands by changing its contents by incrementing by one. The address of the next microcommand is formed every time after reading the basic operating microcommand from the third blocking unit 31. The format of the microcommand of the second recording unit 28 is split into two fields: the first field records the address of the base operational microcommand, in the second field - the number of shift pulses needed to form an operating microcommand. The second address register 29 has two outputs in accordance with the assignment of each field of the second storage unit 28. In the third storage unit 31, all the basic operational microcommands necessary for the formation of the operational microcommands included in the microprogram are recorded. Reading the base operating microcommand from the first output of the third memory of unit 31 and writing it to the shift register 20 ends the first and begins the second cycle of the firmware control device. During the second cycle of the firmware control device, the content of the pulse counter 17 decreases by one for each high frequency clock from second generator output 2 3 clock pulses. In the register 20 shift occurs the formation of the operating microcommand. The zero state of the pulse counter 17 is a sign of the end of the formation of an operational glycocomand from the base through its cyclic shift and resolves read-throughs of the generated operating micro-command from the shift register 20. Reading information from the register. The shift control 20 controls the control trigger 15. The device operates as follows. In the initial state, all elements are in the zero state. The operation code (number) enters through input 32 into register 1, and sets the address of the corresponding memory cell in the first storage unit 3. The 23 clock pulse generator from the first output through delay element 13 in the presence of an enable signal from the output of the third element 10 sets the counter 26 of the address, the buffer register and the register 4 of logical conditions are zero and triggers the first decoder 2. The signal from the first decoder 2 from the corresponding memory cell of the first storage unit 3 reads the code the first microcommand of a regular linear sequence, the code of checked logical conditions and the address code of the first microcommand of the current linear sequence, as well as the reset of address register 1 by the signal from the output of the first storage unit 3. The signal from the generator output the enable signal from the output of the counter 9 microinstructions corresponding to its zero state is fed to the second input of the second block 7 of the elements AND, and records the code of the number following linear sequence in register 1 of the address from the output of buffer register 6. After reading the address part of the microcommand and writing into the counter 9 microcommands the code of the number of microcommands the contents of the counter are different from zero. The signal at the output of the third element And 10 takes a zero value and through the first element -NE 24 opens the second element AND 23. With the same signal from the output of the delay element 12, the control trigger 15 is set, which opens the fifth element 16 with its single output. The signal from the first output of the generator 23 clock pulses through the open second element And 25 zeroing the register 29 addresses and starting the second decoder 27. The signal from the output of the second decoder 27 from the second storage unit 21 reads and information from the corresponding cell and write the contents to the address register 29. The code of the base operating microcommand number from the first output of the register 29 arrives at the first input of the third decoder 30. From the second output of the register 29, information about the number of shifts required to form the corresponding operating microcommand is recorded in the pulse counter 17. At the same time, the contents of the account 17 are different from zero. .

The signal from the output of the generator 2-pulse pulses through the delay element 13 starts the third decoder 30, reset the registrar 20 shift.

From the third storage unit 31, the signal from the output of the third decoder 30 reads the corresponding basic operating microcommand and writes it to the shift register 20.

After the basic operating microcommand is written to the shift register 20 through the open single signal from control trigger 15, the fifth element AND 16 starts shifting the basic operating microcommand in shift register 20 and decreasing the contents of the counter 17 pulses to high frequency clock pulses from the second generator output 23 clock pulses.

During the entire time of the shifts of the basic operating microcommand in the shift register 20, the signal at the element's output. I-YE 18 is equal to one, and it keeps the sixth element AND 19 in the open state, skipping the shift pulses from the output of the fifth element And 16 into the shift register 20 .

After the process of forming the operating microcommand is completed in the shift register 20, as evidenced by the zero signal at the output of the AND-HE element 18, the sixth element AND 19 is closed, and the control trigger 15 is set to the zero state. In this case, the third block 21 of the elements I. opens with a single signal from its zero output. An operational microinstruction, recorded in shift register 20, arrives at the output 34 of the device.

After reading the basic operating microcommand from the third storage unit 31, the contents of the address counter 26 are incremented by one, thereby forming the address of the next microcommand of the sequence, and the contents of the microcode 9 counter decreasing by one.

The next clock pulse from the output of the generator 23 through the open second element And 25 starts the third decoder 30 and clears the shift register 20. Subsequently, the operation of the firmware control device will be reconciled.

After reading the last microcommand of the current sequence, the counter of 9 microcommands is reset, at the output of the third element And 10 a single signal appears, which closes the second element And 25 and opens the Fourth 1.4 and the first 11 Element / Ribbon I.

The signal from the output element 13 of the delay clock pulse from the first

the output of the generator 23 clock pulses reset the register 4 logical conditions and the buffer register b, the counter 26 addresses and start the first decoder 2.

Thus, the introduction of these elements and bonds can significantly improve the efficiency. At the same time, other characteristics, such as functionality and speed, remain unchanged, since the shift operations are carried out with a frequency that is much higher than the frequency of reading information from the storage blocks.

Claims (2)

Invention Formula A firmware control device containing a register of logical conditions, the output of which is connected to the first input of the first block of elements I, the output of which is connected to the input of logical conditions of the buffer register, the output of which is connected to the first input of the second block of elements And whose output is connected to the information input of the first register an address whose operation code input is an input of the device operation code, the output of the first address register is connected to the information input of the first decoder, the output of which is The first address output of the first storage block is connected to the address input of the buffer register, the second address output to the input of the encoder, the output of logical conditions to the information input of the register of logical conditions, and the reset output to the input of the first address register to zero, the second input of the first block of elements And is connected to the input of the logical conditions of the device, the second input of the second block of elements And is connected to the output of the first element And, the first input of which is through the first and second the delay elements are connected to the first output of the clock generator, the second input of the first element I is connected to the output of the third element I, to the first input of the fourth element I, and through the first element NOT to the first input of the second element I, the second input of which is connected to the first input of the clock generator pulses, the output of the second element I is connected to the input of setting the second address register to zero and the starting input of the second decoder, the group of inputs of the third element I connected with the group of outputs of the microinstruction counter, the first Its input is connected to the first output of the encoder, the second output of which is connected to the information input of the address counter, the installation input to zero of which is connected to the installation inputs to the zero of the register of logical conditions, the buffer register, the start input of the first decoder and the output of the fourth I element, and the output of the counter addresses - with the information input of the second decoder, the output of which is connected to the input of the second memory unit, the output of which is connected to the information input of the second address register, the first bit the stroke of which is connected to the information input of the third decoder, the start input of which is connected to the output of the first delay element, and the output of the third decoder is connected to the input of the third storage unit, the first output of which is connected to the counting input of the address counter and the second input of the microscopic counter, characterized by that, in order to increase efficiency, it additionally contains a pulse counter, a shift register, an AND-NOT element and a third block of AND elements, and the information input of an impulse counter is connected to the second the th bit output of the address register, the counting input of the pulse counter — with the output of the fifth element And and the first input of the sixth element And; the first input of the fifth element And is connected to the single output of the control trigger, and the second input. - with the second output of the clock pulse generator, the single control trigger input is connected to the output of the second delay element, and the zero input through the second element is NOT connected to the second input of the sixth AND element and the output of the NAND element, the input group of which is connected to the pulse counter output group , the output of the sixth element I is connected to the first input of the shift register, the second input of which is connected to the output of the first delay element, the third input to the first output of the third recording unit, and the output to the first input to the third The first block of And elements, the second input of which is connected to the zero output of the control trigger, the output of the third block of the And element is the output of the device. Sources of information taken into account in the examination 1. USSR author's certificate number 763898, cl. G 06 F 9/16, 1978. 2. USSR author's certificate according to application No. 2802977 / 18-24, cl. G 06 F 9/16, 1979 (prototype).