SU892739A1

SU892739A1 - Reversible counter

Info

Publication number: SU892739A1
Application number: SU802896550A
Authority: SU
Inventors: Илья Маркович ЛАЗЕР; Геннадий Сендерович Брайловский; Юрий Сергеевич Крылов
Original assignee: Предприятие П/Я А-7438
Priority date: 1980-03-24
Filing date: 1980-03-24
Publication date: 1981-12-23

Description

(5) РЕВЕРСИВНЬЙ СЧЕТЧИК(5) REVERSING COUNTER

Claims

The invention relates to devices of pulsed technology and can be used in automation and computing. A reversible counter is known, which contains bits, each of which contains a counting trigger, and switching elements, the first inputs of which are connected to the outputs of the counting trigger, and the second inputs are connected to control buses Cl. The disadvantage of this reversible counter is a relatively low speed. Also known is a reversible counter, which contains bits, each of which contains the first, second, and third RS-flip-flops, and each bit, except the first, also contains dopol. The main element of the NAND, the first RS-TpH Gerber of the first bit contains the first and second elements of the NAND, the first inputs. which are connected to the outputs of the second and first elements of the IS-NOT of this RS-flip-flop, the remaining inputs of the first and second elements of the IS-NOT are connected respectively to the one and zero outputs of the first RS-flip-flop, the second RS-flip-flop of the first bit contains the third and third the fourth NAND elements, the first inputs of which are connected to the outputs of the fourth and third NAND elements, respectively, the remaining inputs of which are connected by co. respectively, with the single and zero inputs of the second RS flip-flop, the third RS flip-flops of each bit contain the fifth and sixth AND-NES elements, the first inputs of which are connected to the sixth and fifth elements of the IS-NOT, respectively, whose hundredth inputs are connected respectively with zero and single inputs of the third RS-flip-flop, the first RS-flip-flop of each bit, except the first, contains the first and second AND-NOT elements and the first auxiliary AND AND-NO element, the first inputs of the first, second and first AID-1 elements connected with the outputs, respectively, of the second and first auxiliary ements of the AND-NOT,. the remaining inputs of which are connected to the first group of zero inputs of the first RS flip-flop, the second group of zero inputs of the first RS flip-flop are connected with the remaining inputs of the second NAND element, and the single inputs of the first RS flip-flop are connected to the remaining inputs of the first AND-N element of the second RS- the trigger of each bit, except the first one, contains the third and fourth AND-NES elements and the second auxiliary AND NES element, the first inputs of which are connected to the outputs of the fourth and third AND-NAND elements, respectively, the second input of the third AND-NIC elements Dinen with the output of the second auxiliary element AND-NOT, the remaining inputs of which are connected to the first group of zero inputs of the second RS-trigger, the second group of zero inputs of which is connected to the remaining inputs of the fourth element AND-NOT, and the single inputs of the Second RS-trigger soy dinene with the remaining inputs of the third NAND element, the output of the N I element of each bit is connected to the single input of the first RS-flip-flop of the same bit, and the platoons of the first groups of zero YHRDs of the first and second RS-flip-flops of the next bit, second group n the hubs of the circuit are connected to the output of the sixth element I-HE of the previous discharge, the counting input of the reversible counter is connected to the zero inputs of the first and second RS triggers of the first discharge, the output of the first element AND-NOT of each discharge is connected to the single input of the second RS- the trigger of the same bit, the output of the fourth element of the IS-NOT cadcc times is connected to the zero input of the third RS flip-flop of the same bit and in the first bit to the zero input of the first RS flip-flop, and from the rest of the bits with the input of the second group of zero inputs per of the same bit, the output of the second NAND element of each bit is connected to the single input of the third RS flip-flop of the same bit, the output of the first auxiliary element of the NAND of each of the bits is connected to the single input of the third RS- the trigger of the same bit, the zero input of which is connected to the input of the first group of zero 94 inputs of the first RS flip-flop of the same bit and the output of the second auxiliary element AND-NOT of the same bit, the output of the additional element AND-NOT of each bit is connected to the unit the second RS-trigger input The first bit of the first bit of the first RS-flip-flop, the output of the sixth element of the NAND cell, besides the first one, is connected to the first input of an additional NAND element of the same bit, the second input of which is connected with pshnaya Reverse, bus Addition is connected to the inputs of the second groups of zero inputs of the first and second RS-flip-flops of each of the bits, pin Subtraction is connected to the inputs of the first groups of zero inputs of the first and second RS-flip-flops of all bits 21. The disadvantage of this reversible counter is relatively large complexity. The purpose of the invention is to simplify the reversible counter. The goal is achieved by the fact that in the reversible counter containing bits, each of which consists of the first, second and third RS-triggers, and each bit, except the first, also contains an additional element IS-NOT, the first RS-trigger of the first bit Yes, it contains the first and second elements of NAND, the first inputs of which are connected to the outputs of the second and first elements of the NAND of this RS TpHrrepa, respectively, the remaining inputs of the first and second. AND-NOT elements are respectively connected with single and zero inputs of the first RS flip-flop, the second RS-flip-flop of the first bit contains the third and fourth AND-NOT elements, the first inputs of which are connected to the outputs of the fourth and. The third NAND elements, the remaining inputs of which are connected respectively to the single and zero inputs of the second RS flip-flop, the third RS flip-flops of each bit contain the fifth and sixth NAND elements, the first inputs of which are connected respectively to the outputs of the sixth and fifth elements NAND, the remaining inputs of which are connected respectively to the zero and single inputs of the third RS flip-flop, the first RS flip-flop of each bit, except the first, contains the first and second AND-NES elements and the first auxiliary NID elements, the first ones of the first, The second and first auxiliary elements of the NAND are connected to the outputs of the second, respectively, and the first elements of the NAND, the second input of the first element of the NAND is connected to the output of the first auxiliary element of the NAND, the remaining inputs of which are connected to the first group of zero inputs the first RS flip-flop, the second group of zero inputs of the first RS-three hera is connected to the remaining inputs of the second NAND element, and the single inputs of the first RS flip-flop are connected to the remaining -1 I inputs of the first NAND element, the second RS flip-flop of each bit except first It contains the third and fourth elements of the NAND and the second auxiliary element of the NAND, the first inputs of which are connected to the outputs of the fourth and third elements of the NAND, respectively, the second input of the third element of the NAND is connected to the output of the second auxiliary element of the NAND , the remaining inputs of which are connected to the first group of zero inputs of the second RS flip-flop, the second group of zero-inputs of which is connected to the remaining inputs of the fourth NAND element, and the single inputs of the second RS flip-flop are connected to the remaining inputs of the third el NI, the output of the nth element of NI of each, the bit is connected to the single input of the first RS flip-flop of the same bit and the inputs of the first groups of zero inputs of the first and second RS-flip-flops of the next bit, the second groups of zero inputs of which are connected With the output of the sixth element IS-NOT of the previous bit, the counting input of the reversible counter is connected to the zero inputs of the first and second RS flip-flops of the first bit, the output of the first element AND-NOT of each bit is connected to the single input of the second RS flip-flop of the same bit fourth exit The NAND element of each bit is connected to the zero input of the third RS flip-flop of the same bit and, in the first bit, to the zero input of the first RS flip-flop, and in each of the remaining bits to the input of the second zero-input group of the first RS - three geers of the same bit, the output of the second NAND element of each bit is connected to the single input of the third RS flip-flop of the same bit, the output of the first auxiliary element of the NAND of each of the bits is connected to the single input of the third RS flip-flop the same bit, the zero input of which is connected to the input of the first g The group of zero inputs in the first RS trigger of the same bit and the output of the second auxiliary element NAND of the same bit, the input of the additional NAND element of each bit is connected to the single input of the second RS trigger of the same bits as the inputs of the first and the second group of zero inputs of the first RS-flip-flop, the output of the sixth AND-NOT element to 1x bit, except the first one, is connected to the first input of an additional AND-NE element of the same bit, the second input of which is connected to the bus Reverse, Bus Addition is connected to the inputs second groups of zero The inputs of the first and second RS-flip-flops from one of the bits, the Subtraction bus are connected to the inputs of the first groups of zero inputs of the first and second RS-flip-flops of all bits, the first and second additional inputs of the additional AND-NOT elements of each of the bits are connected to the outputs of the second the NAND element and the first auxiliary NAND element of the same bit, and the single inputs of the first RS flip-flop; xdogo of the bits, except the first, are connected to the inverse reverse bus. The drawing shows a block diagram of the counter. A reversible counter contains bits 1, each of which contains the first 2, second 3 and third 4 RS-flip-flops, and each bit, except the first, also contains an additional element IS-HE 5, the first RS-flip-flop 2, the first bit contains the first 6 and second 7 IS-NOT elements, the first inputs of which are connected to the outputs of the second 7 and first 6 elements of the IS-NOT of this RS trigger, respectively, the remaining inputs of the first 6 and second 7 elements. AND-NOT are connected respectively to the single and zero inputs of the first RS flip-flop, the second Rj-flip-flop 3 of the first bit contains the third 8 and fourth 9 AND-NOT elements, the first inputs of which are connected to the outputs of the fourth 9 and third 8, respectively. - NOT, the remaining inputs of which are connected respectively to the single and zero inputs of the second RS-flip-flop 3, the third RS-flip-flops 4 of each bit contain the fifth, 10 and sixth 11 AND-NOT elements, the first inputs of which are connected respectively to the sixth-11 outputs and of that 10 elements AND NOT NOT, Their inputs are connected respectively to the zero and single inputs of the third RS flip-flop 4, the first RS flip-flop 2 of each bit, except the first, contains the first 6 and second 7 H-NOT elements and the first auxiliary element AND-HEN 12, the first inputs of the first 6 and the second 7 and the first auxiliary 12 elements AND-NOT connect to the outputs of the second 7, the first 6 and the first 12 auxiliary elements AND-NOT, respectively; the second input of the first element AND-NOT b is connected to the output of the first auxiliary element AND IS NOT 12, the rest which inputs are connected with the first group of zero inputs of the first RS-flip-flop 2, the second group of zero-inputs of the first RS-flip-flop 2 is connected to the remaining inputs of the second AND-NE 7 element, and the single inputs of the first RS-flip-flop 2 are connected to the remaining inputs of the first element-AND-6 and the second RS The trigger 3 of each bit, except the first, contains the third 8 and fourth 9 AND-NOT elements and the second auxiliary AND-NOT 1 element. 3, the singing inputs of which are connected to the outputs of the fourth 9 and third 8, respectively, of the N – N, the second input of the third NAND element. 8 is connected to the output of the second auxiliary element IS-HE 13, the remaining inputs of which are connected to the first group of zero inputs of the second RS flip-flop 3, the second group of zero inputs of which are connected to the remaining inputs of the fourth element AND-HE 9 trigger 3 is connected to the remaining inputs of the third 8 AND-NOT element, the output of the fifth element AND-NOT 10. Each bit is connected to the single input of the first RS flip-flop 2 of the same bit, and the inputs of the first groups of zero inputs of the first. 2 and the second 3RS triggers of the next bit, the second groups of zero inputs of which are connected to the output of the sixth element AND-NOT 11 of the previous bit,. the counting input 14 of the reversing counter is connected to the zero inputs of the first 2 and second 3 RS-triggers of the first bit, the output of the first element AND-HEN 6 of each bit is connected to the single input of the second RS-flip-flop 3 of that 98 Same bit, the output of the fourth element AND - NO 9 of each bit is connected to the zero input of the third RS flip-flop 4 of the same bit, and, in the first bit, to the zero input of the first RS flip-flop 2, and in each of the remaining bits to the input of the second group of zero inputs of the first RS-triprie 2 of the same bit, the output of the second element AND-NOT 7 of the third bit Yes connected to a single entrance. The third RS flip-flop 4 of the same bit, the output of the first auxiliary. Each of the bits NAND 12 of each of the bits is connected to the single input of the third RS flip-flop 4, the same bit, the zero input of which is connected to the input of the first group of zero inputs of the first RS-trichgera 2 of the same bit and the output of the second auxiliary element AND -NON 13 of the same bit, the output of the additional element AND-NOT 5 of each bit is connected to the single input of the second RS flip-flop 3, the same bit and the inputs of the first and second groups of zero inputs of the first RS flip-flop 2, the output of the AND- element NOT 6 of each bit except the first is connected to the first input. additional NAND 5. the same discharge, the second input of which is connected to the bus Reverse 15, the bus Addition 16 is connected to the entrance. the second groups of zero inputs of the first 2 and second 3 RS-flip-flops of each of the bits, bus Subtraction 17 is connected to the inputs of the first groups of zero-inputs of the first 2 and second 3 KS-flip-flops of all bits, the first and second additional, complement bHbix elements And - NO 5 of each of the bits is connected to the outputs of the second element NAND 7 and the first auxiliary: the NAND element 12 of the same bit, and the single inputs of the first RS-flip-flops 2 ka Dogo from the bits other than the first, soy. Scott) with inverse tire 18 reversal. . Reversible counter works as follows. During the counting in one of the modes (addition or subtraction), the elements 5 are closed by a logic zero signal on the bus 15 Reverse. Before changing the counting mode, the incoming signal of the bus of bus 15 Reverse, depending on the state of the discharge, opens element 5, depending on the state of the discharge. The signal from the output of the open element 5 when changing the operation mode and the dangerous condition of the pre-discharge discharge ensures that the RS-flip-flops are set to confirm the status of the third RS-flip-flop. Thus, eliminating the possibility of a counter failing when reversed. Consider, for example, the operation of the neips of two bits of a reversible counter. In the initial state, these bits are in the 00 state, and on the Addition 16 and Subtraction 17 tires, the signals are added that correspond to the summation mode. Then the shock and the input 14 pulses are naturally summed in the first and second bits. After the arrival of the fifth counting pulse, it is necessary to start the calculation mode. At the time C, the signals on the Reverse buses and the inverse reverse bus 18 are changed. Since the second bit is in the zero state — logic element 5 switches to the logical zero state and causes a change in the state of the single input of the second RS flip-flop 3, and also simultaneously terminates the zero inputs of the first RS flip-flop 2. When the signals on buses are added, Addition 16 and Subtraction 17 at time tj, the zero output of the second RS flip-flop 3 generates a logic zero signal confirming the zero state of the third RS flip-flop 4. Thus, the reverse, in which the logical zero signal is switched to the logical one signal at the input of the second bit, does not cause a change in the state of the second bit output. At time t, the signals on the buses 15 change. and 18, which ensures switching off the logic element 5 and further normal operation of the counter in the subtraction mode. Consider the counter operation when changing the operation mode in the case when the second bit is in a single state, and the input signal is switched when changing the mode from a logical zero to a logical one. This is the situation. takes place in the counter, for example, after the twelfth counting pulse. At the time t, signals are received on buses 15 and 18. Due to the single state of the second bit, the state of the logic element 5 cannot be changed, and the bus 15 signal directly arriving at the single input of the first RS flip-flop. 2, causes the appearance of a logical unit at the output of this trigger and, as a consequence, a transition to the zero state of the second RS flip-flop 3. The processes occurring at the time point C ensure the installation of the first 2 and second 3 RS-flip-flops, which further confirms the status of the third RS-. trig- . At the moment of time tg there is a change of signals on tires 15 and 18. This causes the appearance of a logical zero at the output of the first RS-trnger 2 and confirms the state of the third RS-flip-flop 4. The secondary change of signals on buses 15 and 18 at the time of time tj does not cause any changes in the state of discharge. Thus, in a different initial state of the second bit, the appearance of a logical unit at its input does not cause a failure when changing the operating mode of the meter. When the thirteenth and subsequent counts arrive, the counter operates in the addition mode. The proposed reversible counter provides relatively high speed and reliability at relatively low hardware costs and can be realized on the ICH-1-IE elements by equivalently replacing all H-NOT elements included in the reversible counter. The invention The reversible counter containing bits, each of which contains the first, second and third RS-flip-flops, and each bit, except the first, also contains an additional AND-NOT element, the first RS-flip-flop of the first bit contains the first and second And elements - NOT, the first inputs of which are connected to the outputs of the second and first elements of the IS-NO of this RS-flip-flop, the remaining inputs of the first and second elements of the IS-NOT are connected respectively to the one and zero inputs of the first RS-flip-flop, the second RS-flip-flop of the first bitwin-third and fourth AND-NO elements, first inputs of which are connected to the outputs of the fourth 11 respectively. and the third IS-NOT elements, the remaining inputs of which are connected respectively to the single and zero inputs of the second RS-flip-flop, the third RS-flip-flops of each bit contain the fifth and sixth AND-NOT elements, the first inputs of which are connected respectively to the outputs of the sixth and n In addition, the NAND elements, the remaining inputs of which are connected respectively to the zero and single inputs of the third RS flip-flop, the first RS flip-flop of each bit, except the first, contains the first and second AND-NAND elements and the first auxiliary NAND element, the first the inputs of the first, The second and first auxiliary elements AND-NOT are connected to the outputs of the second and first elements N-NOT, respectively. The second input of the first element IS-NOT is connected to the output of the first auxiliary element NAND, the remaining inputs of which are connected to the first group of zero inputs of the first RS flip-flop. , the second group of zero inputs of the first RS flip-flops is connected to the remaining inputs of the second NAND element, and the single inputs of the first RS flip-flop are connected to the remaining inputs of the first NAND element, the second RS flip-flop of the first digit, first the third and fourth elements of the NAND and the second auxiliary element of the NAND, the first inputs of which are connected to the outputs of the fourth and third elements of the NAND, respectively, the second input of the third element of the NAND, and the rest the inputs of which are connected to the first group of zero inputs of the second RS flip-flop, the second group of zero inputs of which is connected to the remaining inputs of the fourth NAND element, and the single inputs of the second RS flip-flop are connected to the remaining inputs of the third element That I-NOT, the output of the first IS-element of each bit is connected to the single input of the first RS flip-flop of the same bit and the inputs of the first zero input groups of the first and second RS-flip-flops of the next discharge, the second groups of zero inputs of which are connected With the output of the sixth element IS-NAR of the previous bit, the counting input of the reversible counter is connected to the zero inputs of the first and second RS-flip-flops of the first bit, the output of the first element AND-NOT of each bit is connected to the single input of the second RS flip-flop of the same bit Yes, the output of the fourth e The NAND of each bit is connected to the zero input of the third RS flip-flop of the same bit and, in the first bit, to the zero input of the first RS flip-flop, and in each of the other bits to the input of the second group of zero inputs of the first RS - trigger of the same bit, the output of the second element NAND of each bit is connected to the single input of the third RS flip-flop of the same bit, the output of the first auxiliary element of the NAND of each of the bits is connected to the single input of the third RS flip-flop The same as the zero input of which is connected to the input of the first groups of zero inputs of the initial RS-flip-flop of the same bit and the output of the second auxiliary element NAND of the same bit, the output of the additional N-element of each bit is connected to the single input of the second RS flip-flop of the same bit and the inputs of the first and the second group of zero inputs of the first RS-flip-flop, the output of the sixth element AND-NOT of the quit bit, except the first one, is connected to the first input of the additional e-element N-NO of the same bit, the second input. which is connected to the bus Reverse, the bus Addition is connected to the inputs of the second groups of zero inputs of the first and second RS-flip-flops of each of the bits, the bus Subtraction is connected to the inputs of the first groups of zero inputs of the first and second RS-triggers of all bits, characterized in that For the sake of simplicity, the first and second additional inputs of additional AND-NOT elements are each. from the bits of the connector to the outputs of the second NAND element and the first auxiliary element of the NAND of the same bit, and the single inputs of the first RS flip-flops of each of the bits, except the first, are connected to the inverse reverse bus. Sources of information taken into account during the examination 1. USSR author's certificate K 513511, cl. And 03 K 23/00, 1971.

2. USSR author's certificate number 708516, cl. H 03 K 23/24, 1980. (prototype),