SU892734A1 - Reversible absolute value counter - Google Patents

Description

(54) REVERSIBLE COUNTER ABSOLUTE VALUES

. 1 The invention relates to a pulse technique and can be used in equipment of various purposes as a pulse counter, which allows representing numbers with absolute magnitude and sign, in particular, in devices controlling the movement of stepping drives of process equipment for the production of integrated circuits. A reverse pulse counter is known, comprising two input buses, a sign trigger, a reverse pulse counter, elements K, OR, and NOT and a zero state decoder ij. A disadvantage of the known device is its relative complexity due to the presence of the zero-state decoder of the reversible pulse counter. A reverse absolute value counter is known that contains N counting decades, an input bus, a control bus, a reset bus, a NOT element, an EXCLUSIVE OR element, a NOT-OR element, two NAND elements and a trigger whose clock input is connected to the last counting-decade loan output and with the first input of the element NOR, whose second input is connected to the reset bus and to the reset input of the trigger, whose information input is connected to the trigger output terminal and to the first input of the element EXCLUSIVE OR whose second input is connected to the control bus, The output of the EXCLUSIVE OR element is connected to the first input of the first NAND element and, through the NOT element to the first input of the second NAND element, the input bus is connected to the second inputs of the first rf of the second NAND element, whose outputs are connected to the first and second clock respectively the inputs of the first counting decade, the transfer and loan outputs of each counting decade are connected respectively to the first and second clock inputs of the next counting decade, the reset input of each counting decade is connected to the output of the NOT-OR element 12. However, the device named a relatively low accuracy caused by the fact that in passing through the reversible counter zero state is lost one input pulse. The purpose of the invention is to improve accuracy. The goal is achieved by the fact that in the reverse counting absolute values, containing N counting decades, input bus, control bus, reset bus, NOT element, EXCLUSIVE OR element, NOT-OR element, two NAND elements and a trigger, the input of which is connected to the output of the last counting decade loan and to the first input of the NOT-OR element, the second input of which is connected to the reset bus and to the reset input of the trigger, whose information input is connected to the forward output of the trigger EXCLUSIVE OR, the second input which It is connected to the control bus, the output of the EXCLUSIVE OR element is connected to the first input of the first NAND element and, through the element NOT to the first input of the second AND NAND element, the input bus is connected to the second inputs of the first and second AND NAND elements whose outputs connected to the first and second clock inputs, respectively, of the first counting controller; transfer and loan outputs of each counting decade, respectively, connected to the first and second clock inputs of the next counting decade; the reset input of each counting decade, connected to the output element NOR introduced rashiritel pulses input and output connected respectively to the MDM taktvym trigger input and to the input of the first loading of the counting decades, informtsionnye whose inputs are connected to respective generators logic levels.

The drawing shows the electrical circuit of the reversible counter of absolute values.

The device contains counting decades - 1-3, elements AND-NOT 2 "1 and 2" 2, input bus 3, element EXCLUSIVE OR 4, element NOT 5, control bus b, output bus 7, Trigger .8, element NOT-OR 9, the reset bus 10, the expander 11, the generators 12 and 13 logic levels, respectively, one and zero.

Transfer and loan outputs of counting decades and are connected respectively to the first and second clock inputs of counting decades and Is3, the last loan output of which is connected to the first input of the element NOT-IL 9, to the clock input of the trigger 8 and through the expander load of the counting decade 1g1, the reset input of which is connected to the reset inputs of counting decades 1 2 and to the output of the element NOT-OR 9, the second input of which is connected to the reset bus 10 and to the reset input of the trigger 8, the information input of which is connected to the forward output of the trigger 8 and with the first entrance element 4 EXCLUSIVE OR, the second input of which is connected to the control bus 6, the output of element 4 EXCLUSIVE OR is connected to the first input of the NAND element, and to the input of the NOT element 5, the output of which is connected to the first input of the AND-NOT element, the second inputs of the AND elements -NOT 2-2 and connected to the input bus 3, the outputs of the elements AND-NOT 2in1 and connected respectively. With the first and second clock inputs of the counting decade, the generators 12 and 13 logic levels are connected to the corresponding information inputs of the counting decade 1 "1.

The device works as follows.

In accordance with the current states of the control and trigger bus b

8, in the counting decades, is accumulated or reduced. When the contents of the counting decades

 - will be equal to zero, the next information pulse coming from the input bus 3 will pass to the exit of the last counting decade loan 1вЗ and switch trigger 8. Moreover, if the number is in the counting decades. - Irf is positive, the sign register initiates a potential of a minus sign on the output bus 7, and if the number is a negative potential of a plus sign. At the same time, this impulse through the element OR NOT

9 arrives at the reset inputs of the counting decades lei -, confirming their zero value and, at the input of the expander 11, which increases the duration of the incoming pulse to the terminal compared to the duration of the input information pulses. Since the duration of the pulse at the output of the expander 11 is longer than the duration of the loan pulse, after the end of the last, it enters the first counting decade 1 1 1 information set by the generators 12 and 13 of the logic levels at the information inputs of this decade, i.e. code one.

Thus, the state of the reversible count of the absolute values by the time the next information pulse arrives becomes i: 00. ..1, which corresponds to the true value of the information. The process then repeats. The duration of the pulse produced by the expander 11 is selected from the conditions

in 3 an in zann

wax

de v

duration of input inin formational pulses; pulse duration,

zones formed by the pulse expander;

follow-up period,

 in informational impulses; The maximum working clock of the chips used.

The introduction of the pulse expander eliminates the impulse loss when the sign of the number changes, i.e. increases the accuracy of the reverse absolute value counter.

Claims (1)

Invention Formula A reversible absolute value counter containing N counting decades, an input bus, a control bus, a reset bus, a NOT element, an EXCLUSIVE OR element, a NOT-OR element, two NAND elements and a trigger, the clock input of which is connected to the output of the last counting decade loan and the first input of the NOT-OR element, the second input of which is connected to the reset bus and to the reset input of the trigger, whose information input is connected to the forward trigger output and to the first input of the EXCLUSIVE OR element, the second input of which is connected to the control bus, output cient exclusive-OR connected to the first input of the first AND-NO element and; through ale /; f / ment NOT, with the first input of the second NAND element, the input bus is connected to the second inputs of the first and second NAND elements, the outputs of which are connected respectively to the first and second clock inputs of the first counting decade, the transfer and credit outputs of each counting decade are connected respectively to The first and second clock inputs of the next counting decade, the reset input of each counting decade, are connected to the output of the NOT-OR element, characterized in that, in order to improve accuracy, a pulse expander is entered into it, the input and output of which Dineny, respectively, with the trigger input of the trigger and the input of the load of the first counting decade, the information inputs of which are connected to the corresponding generators of logic levels. Sources of information taken into account in the examination 1, USSR author's certificate. №433643, cl. H 03 K 23/00, 1975. 2, -Electronics, 1978, No. 23, p. 67-68 (prototype).