SU868763A1 - Logic unit testing device - Google Patents

Description

(54) DEVICE FOR THE CONTROL OF LOGICAL BLOCKS

The invention relates to computing and can be used to control the logic blocks of the means of computer technology. A device for testing control of digital nodes of a digital computer is known, which contains a memory block, an input block, a test register, comparison circuits, indicators and input signal drivers 1. A disadvantage of the known device is low productivity due to the considerable time spent feeding a large number of dough sets. The number of test sets required for control units using a known device is large, due to the fact that, when the bits of each test set are parallel in time to the inputs of a controlled log of a block containing sequential circuits (triggers), racing situations arise and therefore to eliminate them, each test suite is divided into several elementary tests. Therefore, the test program becomes longer and takes longer to execute. The closest technical solution to the present invention is a device for monitoring electronic equipment blocks, comprising a control unit, a memory unit connected by an input to the first output of the control unit, and the outputs are connected to the first inputs of a recording unit, the second input of which is connected to the second output of the control unit , the test register, the outputs of which are connected respectively to the first inputs of the comparison elements and the first inputs of the switching elements, the second inputs of which are connected to the third outputs of the control unit, three They are connected to the outputs of the monitored block and with the second inputs of the corresponding comparison elements, the outputs of which are connected to the inputs of the control unit 2. However, the device also has low productivity due to the impossibility of combining several elementary tests in time when controlling sequential logic circuits situations. The purpose of the invention is to increase the speed of the device. The goal is achieved by the fact that the device for controlling logical blocks, containing a control unit, has a memory unit connected by its input to the first output of the control unit, and the outputs are connected to the first inputs of the recording unit, the second input of which is connected to the second output 0 of the control unit , the test register, the outputs of which are connected respectively to the first inputs of the comparison elements and the first inputs of the switching elements the second inputs of which are connected to the third outputs of the control unit, the third to the outputs of the monitored unit and with the second inputs of the respective comparison elements, the outputs of which are connected to the inputs of the control unit, a pulse generator, a trigger, a counter, a decoder, the first AND element and the number of test register inputs — the second AND elements — are entered, the first inputs of which are connected to the corresponding outputs of the information recording unit , the second inputs are with co & fSS CTgTfo with the decoder outputs, the outputs with the test register inputs, the first inputs of the decoder are connected to the first outputs of the counter, the second output of which is connected to the third inputs of the elements cf the first input of the trigger, the second input of which is connected to the first output of the control unit, the third input to the fourth output of the control unit, and the output to the first input of the first element I, the second input of which is connected to the output of the pulse generator, and the output to the counter input and the second input of the decoder.

The drawing shows a block diagram of the device.

The device for controlling the logic unit 1 comprises a control unit 2, a memory unit 3, a recording unit 4, a test register 5, comparison elements 6, switching elements 7, a pulse generator 8, a trigger 9, the first element 10, an And counter, a decoder 12, second elements And 13.

The device works in the following way.

The monitored logic block 1 has n terminals for control connections, each of which can be an input or an output. Separation of the outputs to the inputs and outputs is carried out by elements 7, connecting the outputs of the registrar 5 with the inputs, block 1 or disconnecting, the outputs of the register 5 from the outputs of block 1 according to the signals of block 2. The block 3 is memory and contains test words representing the set and .o ,, corresponding to the input boron and reference output reactions of the block .1. The check is carried out by comparing on the elements 6 the output response of the reference block recorded in the memory block 7 with the reaction of the block 1 being monitored.

Before testing, block 2 cites them. A reset pulse, which sets

The rigger 9 is in the O state and this prevents the passage of pulses from the generator 8 through the element 10 to the counter 11. The same pulse selects the first test word in block 3. Simultaneously, block 2 translates elements 7 into positions corresponding to the inputs or outputs of block 1. By the Record signal, block 2 outputs the first test word from block 3 to block 4. The information of the first test word from the outputs of block 4 goes to the first inputs of the And 13 elements which are closed on the second inputs by signals from the decoder 12.

Then, according to the Input signal, the block 2 sets the trigger 9 to the i state, opening the AND 10 element for passing a burst of pulses from the generator 8 to the counting input of the counter Ne. The gate input of the decoder 12. As a result, the decoder 12 at its outputs alternately, one after the other, outputs pulse signals that gate the elements of AND 13, and successively discharge after discharge enters the information of the first test from block 4 through the elements of AND 13 into the register 5, from the outputs the information is fed to the inputs of the monitored unit 1 and the elements 6 of the comparison. The overflow pulse of the counter 11 sets the trigger 9 to the O position, preventing the passage of pulses through the element 10, and produces the same result as the comparison of the elements 6.

In case the output reference information of register 5 coincides with the response of block 1 in all bits, elements 6 through block 2 of control are taken out of block 3 the next check word, and so on, until block 1 is completely verified. In case of non-comparison, at least on one of the elements 6, block 2 issues a signal to block 4 of the prohibitions, stopping this check.

Claims (2)

The successive change in time at the inputs of the monitored block allows to eliminate the ambiguity at its outputs due to racing situations, having a place from one type of blocks 1 to another. In addition, the ability to specify certain sequences of input actions for memory circuits on one test set, which in a known device can be implemented only in a few test sets, makes it possible to reduce the number of test words in a test program. The access time to block 3 for outputting the next test word, which is determined by the low speed of the I / O devices, is longer than the time for successive changes in the states of all bits of the test register, which is provided by high-frequency elements on integrated circuits. Due to this, the speed of the proposed device is higher than that of the known. Thus, the introduction of the generator 8, the trigger 9, the slider 11, the decoder 12, the first 10 and the second 13 elements And allows you to eliminate racing situations when monitoring blocks with memory and, consequently, to increase fast action by combining several elementary test sets . An apparatus for controlling logical blocks comprising a control unit, a memory unit connected by its input to the first output of the control unit, and outputs to the first inputs of a recording unit, the second input is connected to the second output of the control unit, a test register whose output is connected respectively, with the first inputs of the comparison elements and the first inputs of the switching elements, the second inputs of which are connected to the third outputs of the control unit; the third with the outputs of the monitored block and the second inputs Corresponding elements of the comparison, the outputs of which are connected to the inputs of the control unit, characterized in that, in order to improve speed, a pulse generator, a trigger, a counter, a decoder, the first And element and the number of test register inputs are entered in the device And the first the inputs of which are connected to the corresponding outputs of the information recording unit, the second inputs - with the corresponding outputs of the decoder, the outputs - with the inputs of the test register, the first inputs of the decoder are connected to the first outputs} of the counter, the second you Which is connected to the third inputs of the comparison elements and the first input of the trigger, the second input of which is connected to the first output of the control unit, the third input to the fourth output of the control unit, and the output to the first input of the first element And, the second input to which is connected to the output of the pulse generator and the output is to the counter input and the second input of the decoder. Sources of information taken into account in the examination 1. The author's certificate of the USSR 618742, cl. G 06 F 11/04, 197.7. 2. USSR author's certificate No. 598082, cl. G 06 F 11/04, 1976 (prototype).