SU841049A1 - Storage cell for shift register - Google Patents

Description

(54) MEMORY CELL FOR SHIFT REGISTER

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The invention relates to computational and digital measurement technology and may be used in the design of various devices and devices in which information conversion is necessary.

A shift register is known, containing in each bit an RS trigger and three AND elements, a forward and reverse transfer transmission block. This shift register shifts the information and its processing, for example, addition 1.

However, it does not allow multiplication of binary-decimal numbers.

The closest in technical essence to the present invention is a memory cell for a single-phase shift register, made on D-triggers with an internal delay 2.

The lack of a known memory location is the difficulty of performing a multiply operation in binary-decimal code 8-4-2-1.

The purpose of the invention is to expand the functionality of a memory cell by providing an operation of multiplying numbers in a binary-tenth code.

This goal is achieved by the fact that AND elements and decryptors are entered in series in the memory cell for the shift register containing the RS flip-flop and DRS flip-flops and clock bar serially connected, the outputs of the first of which are connected to the R- and S- inputs DRS-tJ) players, the first inputs of the first descrambler are connected to the direct and inverse outputs of the RS trigger and the DRS triggers, the outputs of the second decoder are connected to one of the inputs of the And elements, the other inputs of which are connected to the clock bus, the output of the first element And are connected to the C- DRS Trigger Inputs and the first output of the memory cell, the output of the second element And is connected to the second input of the first decoder and the second output of the memory cell, inverse outputs

5 RS-flip-flops and DRS-flip-flops are connected to the inputs of the second decoder.

The drawing shows a functional diagram of a tagged memory cell.

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Coderp5kit RS-flip-flop I, DRS-flip-flops 2, 3 and 4, decoders 5 and 6, And 7 and 8 elements, RS-flip-flop 9 of the next memory cell, clock bus 10, the outputs of the first decoder 11 -16, direct and inverse outputs of triggers 17-24.

The memory cell operates as follows.

Let the memory cell contain a number in the 8-4-2-1 binary-decimal code. In the event that the decoder 6 implements the function §-4 "8-4-2-1 and has a single signal at the direct output, the clock pulse through the And 7 element passes to the R input of the RS triggers 2-4 and shifts the number

The use of alements And and decoders in the memory cell allows multiplication of numbers in the 8-4-2-1 binary-decimal code by 2, which allows to simplify the technical solution of the information conversion circuit.

Claims (2)

1. Gritsevsky PM and others. Fundamentals of automation, pulse and computer technology. M., “Soviet Radio, 1979, p. 160- 163. 2. Bukreev I.N., and others Microelectronic circuits of digital devices M., “Soviet Radio, 1975, p. 140 (prototype).