SU809143A1 - Device for interfacing with computer system common line - Google Patents

Description

(54) DEVICE FOR COMMUNICATION WITH GENERAL / COMPUTER SYSTEM TRAINER

The low reliability of the multiplex trunk is caused by the fact that the interface blocks are interconnected by the interface buses in series, and powering down at least one computer makes the entire computing system inoperable.

The low capacity of the device is explained by the low speed of the operations of occupying the information bus, establishing communication and data transmission due to the delay of the receiving and transmitting elements of the interface blocks connected in series by the ring interface buses. Data exchange between any pair of computing system devices is performed in multiplex mode in a synchronous manner, i.e. for the transmission of each data word, an operation is performed to occupy the interface information bus. From the point of view of ensuring the greatest throughput, this mode is most effective when combining the exchange of data simultaneously between several pairs of slow-acting devices. For high-speed devices, the effect of increased throughput due to the combination of parallel data exchange between several pairs of devices is virtually eliminated, as the data transfer cycle becomes comparable with the interface operation cycle. Taking into account this factor and the fact that the cycle of the interface in the multiplex mode is increased compared to the selector mode by adding to the transfer time, the occupancy of the information gap and the establishment of communication, for high-speed devices, the effective bandwidth of the interface operating in multiplex mode will be lower than in the selector. In addition, the interface of the known device implements a static system of priority of the sources of the request for the occupation of the information highway. The priority of computing system devices can only be changed due to their physical re-switching, it is determined by the cyclic service discipline and provides optimal throughput only for systems whose devices are characterized by the same intensity of requests for data exchange. When the intensity of requests of individual devices, which have different maximum data transfer rates, changes in time, the effective bandwidth of the interface decreases, ceteris paribus.

The purpose of the invention is to increase the reliability and throughput of the highway.

The goal is achieved by the fact that the device containing the transmitting register, whose input is connected to the input data bus, and the output is connected to the trunk information lines through the group of transmitting amplifiers, the receiving register, the output connected to the output data bus, and the information input through the group of receiving amplifiers to the information busses of the trunk, the address comparison circuit, the first input connected to the output of the address storage node, and the second input to the output of the group of receiving amplifiers, the priority register is entered This is a priority comparison circuit, a sampling node, a control node and a pulse shaper, with the first input of the control node connected to the input of the receiving register and the information input of the priority register, and the first output to the first synchronization output of the device and through the pulse shaper to the control inputs of the register and the receiving register, the first input of the priority comparison circuit is connected to the information lines of the highway, the second input and the output, respectively, with the first output and the input of the sample node, and the third input - with the output of the priority register, the second and third inputs of the sampling node are connected respectively to the device request input and the trunk sampling bus, and the second output is ko. the second input of the control node, the third - the eighth inputs of which are connected respectively to the first and second synchronization inputs of the device, the control input of the device, the first and second bus synchronization bus and the output of the address comparison circuit, the second and third outputs of the control node are connected respectively to the second synchronization output of the device and the control input of the group of transmitting amplifiers, as well as the fact that the control node contains two triggers, four AND elements, an OR element, two NOT elements, a delay element and a group the transmitting and receiving amplifiers, and the zero input and the single pulse input of the first flip-flop are connected

0, respectively, with the first and eighth inputs of the node, a single potential input - with a single potential input of the second trigger and a second input of the node, the fifth input of which is connected to the first input of the first element And, and through the first element

 NOT to the first input of the second element AND, the second input of which is connected to the third input of the node and the second input of the first element AND, the output of which is connected to the first input of the OR element, the second input of which is connected to the single output of the second trigger, the pulse single input of which is connected to the output of the second element AND, the output element OR is connected to the third output of the node and the input of the delay element, the output of which is connected to the first

the input of the group of transmitting amplifiers and through the second element is NOT with the first input of the third element I, the first output of the group of transmitting amplifiers is connected to the sixth

the node input and the first input of the receiving amplifier group, the first output of which is connected to the second input of the third element I, the third input of which is connected to the single output of the first trigger, and the output to the first output of the node and the first input of the fourth element I, the second input of which is connected to the fourth the node input, and the output is the second input of the group of transmitting amplifiers, the second output of which is connected to the seventh input of the node and the second input of the group of receiving amplifiers, the second output of which is connected to the zero input of the second trigger and the second the output of the node, and the fact that the sample node contains a trigger, two elements And, the delay element, the element is NOT, the receiving and transmitting amplifiers, the first input of the first element And is connected to the first input of the node, and the output to the second output of the node and the single input of the trigger the zero input of which is NOT connected to the second input of the second element I and the second input of the node through the element, the output of the trigger through the transmitting amplifier is connected to the third input of the node and the input of the receiving amplifier whose output is connected to the first input of the second element And whose output connected to the first output node and the input of delay element whose output is connected to a second input of the first element I.

FIG. 1 shows the structure of a multi-bus computing system; in fig. 2 block diagram of the device; in fig. 3 and 4 - functional diagrams of synchronization and sampling nodes; in fig. 5 is a timing diagram of the operation of the device.

A multi-computer computing system contains computers (controllers) 1 and devices 2 for interfacing with a common highway, including, for example, common information buses 3, buses (lines) 4 and 5 of the trunk (interface) synchronization, and sampling bus (line) 6. The computer 1 is connected to the device 2 via the input 7 and output 8 data buses, request lines (lines) 9, control buses (lines) 10 and synchronization buses (lines) 11-14.

The interface device 2 contains a group of 15 transmitting and a group of 16 receiving amplifiers, transmitting 17 and receiving 18 registers, address comparing circuit 19, address storage unit 20, priority register 21, priority comparing circuit 22, sampling unit 23, control unit 24, and driver 25 pulses (one-shot).

The control unit 24 comprises triggers 26 and 27, elements AND 28-31, element OR 32, elements NOT 33 and 34, delay element 35, groups of transmitting 36 and receiving 37 amplifiers, the second 38, the eighth 39 and the first 40 inputs of the node and the third 41 node output.

Sample node 23 contains a trigger 42, elements And 43 and 44, delay element 45, element 46, receiving 47 and transmitting 48 amplifiers, first output 49 and input 50 of the node.

The digital symbols in the diagram (Fig. 5) define the signals on the correspondingly marked lines of it and the arrows indicate the sequence of signal changes. In this case, the signal 3 - 1 corresponds to the change of information (data, addresses) on bus 3; The indices 3-2 and 3-3 define, respectively, the identification signals of the end of the exchange and the identification of the address transmitted along with the information on the bus lines 3. Intervals 51-53 correspond to the sequence of operations of the exchange session between a pair of computers. Performing a data exchange session between a computer pair of a multi-computing computer system consists of a sequence of three operations: occupying information volume 3 (interval 5), establishing communication between devices (interval 52), transferring data, and close a session of communication (interval 53).

Devices, pod j4eHHbie to the general highway, work as follows.

When the need to exchange information, such as the i-th computer with the j-th computer, appears, the i-th computer on the bus 7 performs writing to the bits of the high and low parts of the output register 17, respectively, the address codes of the i-th and i - a computer with address identifiers and exchange signs, and on line 9 sets a potential request signal that arrives at the first input of element 44. If information bus 3 is currently busy, the request signal is blocked by the zero potential of the signal on sample bus 6, coming through the receiving amplifier 47 to the input element nA and 44. The request signals of other computers are similarly blocked and stored on lines 9 until the end of the communication session between the computers occupying bus 3 at the moment. With the release of the information bus 3 on line 6, a positive potential appears, which, through element 44 on output 49, allows the trigger signal to be output to the comparison circuit 22 in all devices 2 that have established requests. The priority comparison circuit 22 of this signal starts to perform a time comparison of its own priority code, recorded in register 21, with the code currently arriving via information bus 3. If the code recorded in register 21 is greater than or equal to the code, arriving from the information bus 3, after comparing, the code contained in the priority register is formed on it, and the signal of the end of the comparison is output at the output of circuit 22. If the code in the register 21 is less, then the issuance of the priority code to the information bus 3, as well as the generation of the comparison termination signal at the output of the circuit 22 is not performed. Thus, as a result of a parallel comparison that occurs simultaneously in several devices 2 with requests set up, the largest binary code of the highest priority computer is formed on bus 3. The comparison termination signal is fed to the input 50 of the element AND 43, to the second input of which, through the delay element 45, the starting signal of the comparison circuit is received. When the latter is present, a flip-flop 42 is turned on, the signal from the output of which through the transmitting amplifier .48 sets a zero potential on line 6 and thereby fixes the use of information field 3. The zero signal from the output of the receiving amplifier 47 goes to the second input of the And 44 element and blocks the output from the output 49 of the trigger signal to the circuit 22. The transfer of the trigger signal to the non-null state at the input of the circuit 22 blocks the issuance of a priority code to the information bus 3. The operation of the occupation of the information zone 3 is completed. The communication establishment operation is performed as follows. The signal at the output of the element And 43, formed as a result of the operation of occupying the information bus 3, at input 38 turns on the triggers 26 and 27 of the node 24. The signal at the output of the trigger 27 through the element OR 32 at the output 41 goes to the control input of the group 15 of transmitting amplifiers . In this case, all the information recorded in register 17 (addresses, indications) of the i-ro device 2, via information bus 3 and through a group of 16 receiving amplifiers arrives at the information inputs of the register 18 of all devices 2. Address code of the jth computer and address sign also goes to the first input of the address comparison circuit 19. When the incoming address code coincides with the code in the address storage node 20, a signal appears at the output of circuit 19, which at input 39 turns on trigger 26 (in this case, j-ro device 2). Simultaneously with this sequence of actions, the output signal of the OR element 32 of the 1st device 2 through the delay element 35 and the troupe of 36 transmitting elements through the synchronization line 4 goes to the first inputs of the groups 37 of the receiving amplifiers of all devices 2, and through the element HE 34 to the first input of the element . And 30. A positive signal from the first output of a group of 37 receiving amplifiers arrives at the second input of the element AND 30, the third input of which receives the output signal of the trigger 26. Thus. a single signal at the output of the element 30 and Vits is only in the J-TOM device 2. The output signal of the element 30 is fed to the first input of the element 31 and the line 11 starts the driver 25 and causes an interruption of the -th computer. At the output of the driver 25, a blocking pulse is written to the register 18- address codes received from a group of 16 receiving amplifiers. After the interrupt is executed, the j-th computer reads the contents of register 18 and performs an analysis of the information received. In the case of being ready to perform the exchange, the j-th computer on line 13 generates a confirmation signal, which through element 31, group 36 of transmitting amplifiers, via line 5 synchronization goes to the second input of group 37 of receiving amplifiers of all devices 2. Signal from the second output of group 37 the receiving amplifiers through line 14 are fed to all computers (and controllers) of the computing system, but are perceived only by the ith computer. This signal is a confirmation for the i-th computer that on the j-th computer, the address information of the request is perceived. At the same time, the trigger 27 of the i-ro device 2 turns off, which transfers the signal on line 4 to its original position and stops issuing address information to bus 3. The transition of the signal on bus 4 to its original position through a group of 37 receiving amplifiers, elements AND 30.31 j-ro device 2 blocks the issuance of a signal confirming the issuance of information on line 5. Changing the state of line 5 through a group of 37 amplifiers on line 14 is perceived by both computers as a signal to terminate a communication establishment operation. The data transfer operation can be performed in synchronous and asynchronous modes. In synchronous mode, data transmission from a computer data source is performed without waiting for a confirmation signal from a computer data receiver. The mode and direction of data transmission is encoded by bit signs transmitted via bus 3 along with the address information. If the i-th computer is the source of the transmitted data. This synchronous data transfer operation is performed as follows. After an i-a computer establishes a communication operation, on line 7 it records a data word in register 17, and on lines 5 and 12 it sets, respectively, a potential signal for establishing a synchronous mode and a strobe pulse of fixed duration. The signal on line 5 arrives at the first input of the AND 28 element and through the NO 33 element to the first input of the AND 29 element. At the same time, the strobe pulse through the AND 28 element and the OR 32 element at output 41 commutes a group of 15 transmitting amplifiers and installs on the information bar 3 like data. At the same time, a strobe pulse is output through delay element 35 and group 36 of transmitting amplifiers of i-ro device 2 via line 4, which, through group 37 of receiving amplifiers and element 30 of j-ro device 2, starts a single vibrator 25. The signal from the one-shot input 25 writes the data word to the input register 18 of the j-ro device 2. The signal on the bus AND the j-th computer reads the data word and the single-word transfer operation in synchronous mode ends.

In asynchronous mode, a data word transfer session is performed using an acknowledgment signal generated by the data receiver on line 5. The data source computer on line 7 records the data word to register 17, zero potential is set on line 10, and - a potential gating signal, which, coming from a computer via line 12 in element 28, is blocked, and through element 29 includes a trigger 27, the output signal of a trigger 27 through element OR 32 on output 41 permits the issuance of 3 data words to the bus, and delay element 35 peredayush.ih group 36 element sets the potential on the line 6 a signal gating. All other data word transfer operations in asynchronous mode are performed similarly to the transmission of address information (Fig. 5, position 3-3) during the communication operation.

In contrast to the well-known device, in the proposed data exchange system, besides the multiplex one, the selector data transfer mode, which differs from the multiplex one, is possible in that in one communication establishment session not one, but a group (array) of data words is transmitted. The end of the stage of data exchange between a pair of computers in the proposed interface, both in the selector mode and in the multiplex mode, is performed by a sign of the end of the exchange transmitted via bus 3 together with the last data word. The signal of the indication of the end of the exchange from the output of the group of 16 receiving amplifiers resets the trigger 26 and turns off the synchronization node. At the same time, the sign of the end of the exchange is perceived by the computer along with the data word.

Changing the priority of the computer in the system without physically re-switching devices 2 can be performed by changing the contents of the priority register 21. The entry of priority codes into registers 21 can be performed via information bus 3 on a computer that performs the functions of a computer system manager. The writing of priority codes from the dispatcher computer to the registers 21 of the remaining computers and system controllers is performed in the same way as data transmission. At the same time, the priority code transmitted via the information bus 3 is accompanied by a corresponding sign forming the recording signal of the received priority code in the register 21 and the signal for the end of the exchange. Before transmitting each priority code, an operation of establishing a connection between the corresponding computer and the computer controller is performed. All operations for establishing a connection and changing the contents of the device priority registers 21 are performed sequentially for all computers for one bus 3 occupation session.

The transmitting amplifier 48 and each element in groups 15 and 36 perform signal shaping in terms of power and coordination with cable connections. The transmitting amplifier is an inverter with an open collector of an output transistor and can be implemented by any of the known methods, in particular a logical element NOT with an open collector in an integrated design. The parallel connection of several transmitting amplifiers to one line makes it possible to form a signal on this line in accordance with the function of an OR gate with inversion. In this case, the power disconnection of the transmitting element does not affect the state of the line to which several such amplifiers are connected. As

, receiving amplifiers can be used with conventional logic elements with a large input impedance.

Thus, the device allows to increase the reliability of the line and increase its throughput.

0

Claims (3)

Invention Formula  . A device for interfacing with a common trunk of a computer system, containing a transmitting register, whose input is connected to an input data bus, and an output — through a group of transmitting amplifiers, is connected to informational bus lines, a receiving register, an output connected to an output data bus, and an information input through a group of receiving amplifiers to the trunk information buses, an address comparison circuit, the first input connected to the output of the address storage node, and the second input to 5 to the output of a group of receiving amplifiers, inconsistent with the fact that, in order to increase throughput and reliability, a priority register, a priority comparison circuit, a sampling node, a control node and a pulse shaper are entered into it, the first input of the control node is connected to the input of the receiving register and the information input of the priority register, and the first output to the first synchronization output of the device and through the pulse shaper to the control inputs of the priority register and the receiving register, the first input of the comparison circuit prior the power supply is connected to the information buses of the trunk, the second input and output are respectively with the first output and the input of the sample node, and 0 the third input - with the output of the priority register, the second and third inputs of the sampling node are connected respectively to the input of the device request and the trunk sampling bus, the second output - to the second input of the control node, the third - the eighth inputs of which 5 are connected respectively to the first and second synchronization inputs of the device, the control input of the device, the first and second synchronization bus lines and the output of the address comparison circuit, the second and third outputs of the control node are connected respectively to the second synchronization output of the device and the control input of the group of transmitting amplifiers. 2. The device according to claim 1, characterized in that the control node contains two triggers, four AND elements, an OR element, two NOT elements, a delay element, and groups of transmitting and receiving amplifiers, the zero input and the single pulse input of the first trigger connected to the first and eighth inputs of the node, a single potential input - with a single potential input of the second trigger and a second input of the node, the fifth input of which is connected to the first input of the first element AND, and through the first element NOT to the first input of the second element whose second input is connected to the third input of the node and the second input of the first element AND, the output of which is connected to the first input of the OR element, the second input of which is connected to the single output of the second trigger, the pulse single input of which is connected to the output of the second element AND, the output of the OR element with the third output of the node and the input of the delay element, the output of which is connected to the first input of the group of transmitting amplifiers and through the second element NOT to the first input of the third element And, the first output of the group of transmitting amplifiers with one with schestym input node and the first input group of reception amplifiers, a first output of which is connected to the second input of the third AND gate, the third input of which is connected to the unit if vy3 May 6 the first trigger and the output to the first output of the node and the first input of the fourth element I, the second input of which is connected to the fourth input of the node, and the output to the second input of the group of transmitting amplifiers, the second output of which is connected to the seventh input of the node and the second input of the group of receiving amplifiers, the second output of which is connected to the zero input of the second trigger and the second output of the node. 3. The device according to claim. 1, characterized by the fact that the sample node contains a trigger, two elements And, the delay element, the element NOT, the receiving and transmitting amplifiers, the first input of the first element And connected to the first input of the node, the output - with the second output of the node and the single input of the trigger, the zero input of which is NOT connected to the second input of the second element AND and the second input of the node, the output of the trigger through the transmitting amplifier is connected to the third input of the node and the input of the receiving amplifier whose output is connected to the first input of the second element , the output of which is connected to the first output of the node and the input of the delay element, the output of which is connected to the second input of the first element I. Sources of information taken into account in the examination 1. USSR author's certificate number 444062, cl. G 06 E 9/00, 1972. 2. Vishnevsky Yu. L. Multiplexna trunk of a computer complex. Sat “Computing Technique, Novosibirsk, 1976, p. 21-35. 38