SU807290A1 - Microprogramme-control device - Google Patents

Description

(54) FIRMWARE CONTROL DEVICE

This invention relates to a computational technique, in particular, to microprogrammed control devices. A microprogramming control device is known that contains a microinstructions memory unit, microinstructions register), and an microinstructor address register of the microscopic commands 1. The drawback of the device is the need for a larger number of return registers and elements of connection of these registers with the register of the address of micro-commands when organizing a return from the microprograms, which leads to unnecessary expenditure of equipment. The closest in technical essence to the proposed is mnkroprogrshshnoe control device comprising memory mikrokoman Kzoizhul which are connected to the input of the register microinstruction, an address register microinstruction, which outputs Th reeg deishfrator address microinstruction rdklyucheny to the inputs of the memory kshkrokokand, switch, information output of which are connected to the first group of inputs of the register of the address mik.rok (4aids, a microcommand decoder, whose inputs are connected to the first group of outputs of the register of microcommands, The second memory register is connected to the switch's control input, and the second group of register outputs is connected to the second command of the micro-command address register. The known device uses an encoder, a reversible current driver unit to store and read return addresses from micro-subroutines. This uses the regeneration register, the block of amplifiers of reading, the decoder of the address of the operating memory, and also a part of the memory volume of micro-instructions for controlling the specified equipment 2. The disadvantage of the device is the need for a large amount of equipment. The aim of the invention is to reduce equipment. The goal is achieved by the fact that in the firmware control device containing a microinstructions memory block, the input of which is connected to the output of the microinstruction address decoder, and the output is connected to the input of the microinstruction register, the output of which command code

connected to the information input of the micro-command decoder, the control output of the micro-register register is connected to the control input of the switch, and the output of the functional sample is connected with the address input of the micro-command address register, the bit output of which is connected to the micro-command address decoder, and the information register register and micro-command address is connected to the information output of the switch, the RAM block, the output of the functional selection of the register of the shskrocommands is connected to the address input of the register of the address of the RAM, The main input of which is connected to the first output of the micro-command decoder, the control input of the RAM block is connected to the second output of the micro-command decoder, the third output of which is connected to the control of the micro-command address register, the output of memory module 1 of the front-end command is connected to the first information switch input The second information input of which is connected to the output of the RAM, whose information input is connected to the information output of the switch.

The drawing shows the block diagram of the device.

The device contains a block of memory of micro-commands 1, a register of 2 micro-instructions, a register 3 of the address of the operational memory, a block of 4 operational commands, a decoder of 5 micro-commands, a decoder 6 of the address of micro-commands, a register 7 of the address of micro-commands, a switch 8, outputs 9-11 of the register of micro-commands, outputs 12 -14 decoder microinstructions. Output 9 is the control field output, the control switch, output 10 is the field of the command code, output 11 is the output field of the functional sample used to select the memory address and the high-order address bits of the next microcommand.

The device works in the following way.

Microcommands are selected from a block.

1pami micro-commands through the decoder 6 addresses of micro-instructions at the address stored in the register 7 addresses of the micro-command, and poured into the register

2 microscopes. The selected microcommand is encoded in the decoder of 5 microcommands and generates signals that control the recording of information in register 3 of the memory address,

in block 4 of the RAM and in the register 7 addresses of microinstructions.

The address of the next micro-command is formed in register 7 of the micro-command address. The contents of register 7 of the microinstructions by the signal from the output 11 of the decoder 5 microcommands increases by one when all

micro-commands, except for the micro-command of unconditional transition and the micro-command of conditional branching.

If the unconditional transfer microcommand or conditional branch microinstruction is executed, then the microcommand addresses register 7 contains the high order bits of the next microcommand from the output 11 of the register of 2 microcommands, and the lower bits through the switch 8 from the microprogram memory block 1 in the presence of a logical zero at the output 9 of the register 2 microinstructions or from the block 4 of the RAM in the presence of a logical unit. Moreover, the lower-order bits of the next microcommand address are selected from the 4th RAM memory block defined by the 3th RAM address register, or from the microcommand memory 1 cell, the address of which is incremented by 1, relative to the unconditional branch or conditional branching address. In the latter case, the address code entered in the microinstructions register is not decoded.

When building a firmware, a situation often arises when firmware A includes microprogram B as a microsubprogram, which in turn contains firmware C, and so on.

Two microprograms C and D will be considered i-ranks if they cannot be B, one inside the other and not: contains F1 microprograms of rank i and above.

Return registers require as many cells as there are ranks in organized micro-subprograms. If it is necessary to refer to the i-th rank micro subprogram immediately before the micro subprogram, the microinstruction is executed. 4 RAM, defined by the register 3 addresses of the RAM, the return address code coming from the cell of the microcodes memory 2, the address of which is increased by one itelno address microinstruction Loading RON. In the latter case, the return address code stored in the microinstructions register is not decoded.

Claims (2)

To exit the microsubprogram after executing the last microcommand, the microsubtrade should select microx 1 command. Select RON, str by entering information from outputs 11 of register 2 microcommands into the RAM address register 3. and microcontrol of unconditional transition or microcommand conditional branch with a single signal on the output. 9 registers of 2 microinstructions. In register 7, microcommand addresses put the upper half of the addresses of the next microcommand from outputs 11 of the register of 2 microcommands, while the lower bits of the address dcr are a mutator 8 from the cell 4 of the RAM, which is determined by the perHC 3 of the memory address. Thus, in the register of 7 addresses of microinstructions, the address of the microcommand is formed, to which it is necessary to return. The invention allows a significant gain in hardware for processes in which the same microprogram sections can be allocated. The remaining volume is used for current storage of constants, signs of states, error codes. At the same time, there are no communication elements, an encoder, a regeneration register, a reversible current driver unit, a reading amplifier unit, a memory address decoder. Dimensions decrease, reliability increases. Invention Microprogrammed control device containing roco commands memory block whose input is connected to the output of the microinstructor address decoder, and output to the microcommand register input, output of the command code of which is connected to the microcomand information decoder input, output of the microcommand register control output to the control input switchboard, and the output of the functional sample - with the address input register of the microinstruction address, the bit output of which is connected to the input of the microinstruction address decoder, and inform A microcontrol address register input is connected to a switch information output, a RAM block, characterized in that, in order to reduce hardware, the output of a microcommand register function sample is connected to an address address register address of the RAM memory, the control input of which is connected to the first output. the microinstructor decoder, the control 1 input of the RAM block is connected to the second output of the microinstructor decoder, the third output of which is connected to the control input of the microcir address register Mende, yield microinstruction memory unit is connected to a first data input switch, a second information input connected to the output of the operational memory krtorogo An information input is connected to the data output of the switch. Sources of information taken into account during the examination 1. Kasse. Firmware management, kN. 1. World, 1973, p. 38 and 43, fig. 2.1, 2.3. 2. USSR author's certificate number 519711, cl. G 06 F 9/16, 1974 (prototype).