SU798857A1

SU798857A1 - Exponent-computing device

Info

Publication number: SU798857A1
Application number: SU782709184A
Authority: SU
Inventors: Владимир Дмитриевич Байков; Сергей Абрамович Селютин
Original assignee: Организация П/Я Х-5263
Priority date: 1978-12-26
Filing date: 1978-12-26
Publication date: 1981-01-23

Description

1one

Изобретение относитс к вычислительной технике и может быть использовано в ЦВМ, работающих в позиционной системе счислени с фиксированной зап той, дл аппаратурной реализации элементарных функций.The invention relates to computing and can be used in digital computers operating in a fixed-position positional number system for instrumental realization of elementary functions.

Известно устройство, которое содержит регистры, сумматоры, ПЗУ констант , счетчик шагов, схему сравнени , вентили и может быть использовано дл вычислени экспоненты 1.A device is known which contains registers, adders, constant constants, a step counter, a comparison circuit, gates and can be used to calculate the exponential 1.

Недостатком этого устройства вл етс нерегул рность структуры и наличие сложчых блоков - счетчиков и схем сравнени .A disadvantage of this device is the irregularity of the structure and the presence of complicated blocks — counters and comparison circuits.

Наиболее близким по технической сущности к предлагаемому вл етс устройство дл вычислени экспоненты , содержащее первый, второй и третий сдвигающие регистры, вычитатель сумматор, причем первый вход устройства соединен с первым входом первого регистра, выход которого соединен с первым входом вычитател , второй вход вычитател соединен со вторым входом устройства, управл ющий вход вычитател соединен с третьим входом устройства, а его выход - со вторым входом первого регистра и с .первым выходом устройства, четвер ,тый и п тый входы устройства подключены к управл ющим входам сумматора и второго регистра соответственно, шестой вход устройства соединен сThe closest in technical essence to the present invention is a device for calculating exponents, containing first, second and third shift registers, a subtractor adder, the first input of the device connected to the first input of the first register, the output of which is connected to the first input of the subtractor, the second input of the device, the control input of the subtractor is connected to the third input of the device, and its output is connected to the second input of the first register and the first output of the device, the fourth, fifth and fifth inputs of the devices are connected to the control inputs of the adder and the second register, respectively; the sixth input of the device is connected to

первыми входами второго и третьего регистров, выходы которых соединены со входами сумматора, выход сумматора соединен с первыми входами второго и третьего регистров и со вторымthe first inputs of the second and third registers, the outputs of which are connected to the inputs of the adder, the output of the adder is connected to the first inputs of the second and third registers and the second

выходом устройства 2.device output 2.

Недостатком устройства вл етс низкое быстродействие,которое опре:дел етс большим числом шагов, необходимых дл вычислени экспоненты.The drawback of the device is the low speed, which is determined by the large number of steps necessary to calculate the exponent.

При обработке п-раэр дных дес тичных чисел количество шагов имеет пор докDuring the processing of single-decimal numbers, the number of steps is of the order of

иand

10ten

Цель .изобретени - повышение быстродействи устройства.The purpose of the invention is to increase the speed of the device.

Claims

The goal is achieved by the fact that the device for calculating exponentials, containing the first, second and third registers, the subtractor and the adder, the first input of the device connected to the first input of the first register, the output of which is connected to the first input of the subtractor, the second; the input of the device, the control of the subtractor vhbd is connected to the third input of the device, and its output is connected with the second input of the first register and with the first output of the device, the fourth and fifth inputs of the device are connected to the control input By the adder and the second register, respectively, the outputs of the second and third registers are connected, respectively, to the first and second inputs of the adder, the output of which is connected to the first inputs of the second and third registers and to the second output of the device; the memory unit is connected to the second inputs of the second and third registers, and the control unit: the first input is connected to the sixth input of the device, the other input of the memory unit is connected to the output of the address register, the input of which is connected to the first input of the device roystva The drawing shows a block diagram of the proposed device. It contains the first, second, third, fourth, fifth and sixth inputs. Devices 1-6, first, second and third registers 7,8 and 9, subtractor 10, adder 11, memory block 12 (ROM), register 13 addresses, the first and second outputs of the device 14 and 15. The device operates as follows. First, the device receives an argument at input 1, its older part is sent to register 13, and the younger part is sent to register 7. Then, from an external control device (not shown) through input 6, the control input of unit 12 receives a signal sending the registers 8 and 9 of the value of the exponent corresponding to the value of the higher part of the argument. Thereafter, an iterative exponent calculation process begins. The next calculation step begins with an analysis of the sociological register 7. For this, the sign bit of register 7 at output 14 goes to the control unit. If the contents of register 7 are negative, then the calculation stops and the exponent value is read from register 9 on output 15. If the contents of register 7 are positive, then the value 1 is fed from control unit at input 2, and input 3 to control input of subtractor 10 is fed a signal decreasing the contents of register 7 by a unit of lower order. At the same time, input 5 to the control input of register 8 receives a signal that shifts register 8 by ft bits to the right. In the next clock cycle, at input 4, the control input of adder 11 receives a signal that adds the contents of registers 8 and 9 and sends the result of the addition to these registers. This completes the next calculation step and proceeds to the next calculation step. The effectiveness of the invention is to increase the speed of the device by reducing the number of steps in calculating the exponent. An apparatus for calculating an exponential comprising first, second and third registers, a subtractor and an adder, the first input of the device connected to the first input of the first register, the output of which is connected to the first input of the subtractor, the second input of the subtractor connected to the second input of the device the subtractor is connected to the third input of the device, and its output: to the second input of the first register and the first output of the device; the fourth and fifth inputs of the device are connected to the control inputs of the adder and The first register, respectively, the outputs of the second and third registers are connected respectively to the first and second inputs of the adder, the output of which is connected to the first inputs of the second and third registers and to the second output of the device, characterized in that, in order to improve the speed of the device, a block is added to it memory and address register, the output of the memory block is connected to the second inputs of the second and third registers, and the control input is connected to the sixth input of the device, another input of the memory block is connected to the output of the register The country of the address whose input is connected to the first input of the device. Sources of information taken into account in the examination of 1 .. Patent of Great Britain .№ 1014391, class. C 4 A, published. 1972.

2. Japanese Patent No. 50-24211, Cl. 97 (7) EZ, published. 1975 (prototype).