SU546890A1 - Device for calculating elementary functions - Google Patents

Description

one

The invention relates to the field of computer technology and can be used to create digital computers that perform the calculation of elementary functions by hardware.

A device for calculating atomic functions 1 is known, which contains an equating unit and a one-way memory unit. A disadvantage of the known device is the low speed in calculating the function of Sina and Coscc.

Closest to the proposed invention is a device for calculating elementary functions 2, comprising a control unit, a step counter, registers, a subtractor and a one-way memory unit.

The disadvantage of such a device is the inability to directly calculate the functions, Since and Cosa, as basic ones. This leads to the need to develop appropriate programs for these functions, which requires a significant investment of time and equipment for the implementation of programs.

The aim of the invention is to create a device for directly calculating the functions of K-, Sina and Cosa, as basic, i.e., expanding the functional capabilities of the device. In this case, all functions are calculated by a single inertial scheme, which allows reducing hardware costs in the control device and increasing the speed of the device.

The goal is achieved by adding a comparison block, iteration counter, character register, modulo two adder, and OR element, the first input of the one-way memory block is connected to the first output of the control unit, and the output to the first information block. the input of the pseudo-delimiter register, the second input of which is connected to the first information bus, and the third input - to the output of the adder - subtractor and the first input of the register of the dividend, the second input of which is connected to the second information bus, and the output to the first the comparison block, with the first input of the subtractor and the information input of the modifier register, the control input of which is connected to the second output of the control unit, and the output with the second input of the adder - the subtractor, the third input of which is connected to the output of the pseudo-divider register and the second input of the block the comparison, the output of which is connected to the first input of the control unit, the third output of which is connected to the first 3 control inputs of the pseudo-private register and the register of the characters and the sign bit of the register of the dividend, the fourth one with the first input of the modulo adder two, the fifth output with the first inputs 5 lower bits of the pseudo-part register and the character register and the control input of the dividend register, the sixth output with the input of the step counter, the seventh output with the first input of the P1LI element and the second the input of the younger-10 of our pseudo-partial register register, the eighth output - with the second input of the OR element and the first installation input of the lower digit of the register of characters, the second installation input of which is connected to the output 15 of the sign bit of the register of the dividend, and the output from the second modulo-two input, the output of which is connected to the fourth input of the subtractor - subtractor, the low-order output of the pseudoparticle register 20 is connected to the second input of the control unit, the third input of which is connected to the output of the iteration counter, the input of which is connected to the output of the OR element, the fourth input the control unit is connected to the output of the counter 25 steps. The drawing shows a block diagram of the proposed device, where: I-first information bus (for recording information into the re-30 of the splitter / pseudomodible /, the first input); 2 - the second information bus (for recording information in the register of the dividend / product /, the second input); 3 is a one-way memory unit (for storing 35 constants); 4 - pseudo-delimiter register 5 - comparison unit; 6- adder-subtractor; 7 - modifier register; 8 - register of the dividend (product); 9 is the sign bit of the register 40 (product); 10 - the register of characters (digits of the pseudo-partial / pseudomultiplier /); 11 - the lowest bit of the register of characters; 12 - pseudo-part register (pseudo-multiplier); 13 - low-order bit of the pseudo-45 th register (pseudo-multiplier); 14 - modulo adder; 15 - iteration counter; 16 - element OR; 17 — control unit; 18 is the output of the control device for transmitting a change sign of the conversion signal; 19-50 the output of the control unit for transmitting the addition (subtraction) signal “1 to (from) the low-order bit of the pseudo-partial (pseudomultiplier) register; 20 - step counter; 21-output of the control unit for transferring the signal of addition (subtraction) "1 to (from) the contents of the step counter; 22 shows the output of the control unit for transmitting the shift signal to the right of the registers 8, 10 and 12; 23- control device output for transmitting 60 a shift signal to the right of modifier register 7; 24 shows the output of the control device for transmitting the next-constant sampling signal from the persistent storage device; 25 is the output of the control unit for 65. 4 transmit signal shift left registers 8, 10 and 12; 26 is the output of the control unit for transmitting the sign set and redisplay signal. Below is a description of the operation of the device for the case of the decimal number system and, however, the proposed device can operate with an arbitrary value of the iw counting system. When calculating the function of the proposed device works as follows. The values x and y entering inputs 1 and 2 are recorded with their signs in registers 4 and 8. Before the pseudo-division process starts, the contents of iteration counter 15 and step counter 20 are zeroed out, and at output 26 of control unit 17, the signal LOG 1, providing pseudo-sharing mode. At the beginning of each step in which the next pseudo-partial digit is calculated, the contents of the sign bit 9 of the divisor register 8 are sent to the low-order bit 11 of the 10 character register. To modify the output, the output of the divisible register 8 is connected to the input of the modifier register 7, to the shift output which receives a signal from the output 23 of the control unit 17. The amount of shift of the register 7 is determined by the contents of the step counter 20. The outputs of the registers 8 and 7 are connected to the inputs of the adder-subtractor 6, the output of which is connected to the input regis Tra 8, for fixing a new value in it, divisible with its sign. The outputs of registers 7 and 4 are connected to the inputs of the adder - subtractor 6, the output of which is connected to the input of register 4, to record in it the new value of the pseudo-divider with its own sign. The output of the low bit 11 of the register 10 is connected by its input of the adder 14 to set the mode of adhesion or subtraction in the adder - subtractor 6. After calculating the new values of the pseudo-divider and the dividend at the output 19 of the control unit 17, the signal is added, adding 1 to the youngest bit 13 of the register 12. The process continues until the output of the comparison block 5 does not give a signal that the contents of register 8 are less than or equal in absolute terms to the contents of register 4, after which the content of the lowest time is analyzed row 13 of register 12 by control unit 17 for parity; for an odd value of the contents of bit 13, the pseudo-part digit is considered to be calculated, and for an even value of the contents of bit 13, another iteration is performed. After calculating the next digit of the pseudo-part (each digit is less than or equal to 9), the contents of the iteration counter 15 are checked; if the contents of the iteration counter 15 is less than "9, then the output 18 of the control unit 17 is a signal, making a real change in the sign of the transformation. Further iterations continue with the difference that at output 19 of the block

Control 17 does not generate a signal to add "1 to the low-order bit 13 of register 12. The process continues until the contents of the counter become equal to" 9. Before starting the calculation of the next digit of the pseudo-part at the output 25 of the control unit 17, a signal appears that shifts the registers 8, 10, 12 to the left, and at the output 21, the control unit 17 appears the signal to add "1 to the contents of the counter of steps 20, output which is connected to the input of the control unit 17; the contents of iteration counter 15 are zero. The pseudo-division process described continues until all pseudo-partial digits are calculated. At the end of the pseudo-division, register 4 contains the value, where K is a pre-calculated constant.

When calculating the functions of Sina and Cosa, the device works as follows. The value of X, fed to input 2, is written to register 8 with its sign. This is followed by a pseudo-division process for constants of the form lO-arctg 10, which differs from the usual division in that before calculating each digit of the pseudo-private in the register 4 a new constant is written from the one-way memory block 3 using the signal at the output 24 of the control unit 17. The alternating pseudo-particle, represented only by odd numbers, is formed in the same way as the process described above when calculating the function ./ (The difference is that additional alternating sign iterations are not performed. At the end of the process The division in register 12 contains a pseudo-part. Pseudo-multiplication and the resulting pseudo-part (pseudo-multiplier) occur similarly to the pseudo-division described above in calculating the function. The difference is that the output "26 of the control unit 17 providing the mode of pseudo-decomposition. the next digit of the pseudo-part at the output 19 of the control unit 17 appears the subtraction signal "1 from the low-order bit 13 of the register 12. Multiplication by the next digit of the pseudo-partial ends when resetting and 13, whereupon analysis of the contents is performed iterations counter 15. If it is not equal to "9, the alternating iterations are performed. For this purpose, at output 18 of control unit 17, a change in sign of the conversion appears. Alternate iterations are performed until the contents of iteration counter 15 become equal to "9. Before the next pseudo-multiplication step begins, the registers 8, 10 and 12 are shifted to the right by the signal at the output 22 of the control unit 17. At the end of the pseudo-multiplication, register 4 contains the value / C-Cosa, and register 8 contains the K-Sina value.

Claims (2)

1. Copyright certificate C SSR Aib 404082, M. Cl.2 G 06F 7/38, publ. 06.16.72. 2. / VM, Jornal of Research and Development V. 6, No. 2, 1962, pp. 210-216.