SU787238A1 - Digital code decoder - Google Patents

Description

one

The invention relates to railway traffic mathematics and is intended for use in numerical code auto-locking and automatic locomotive signaling.

A numeric code decoder is known that contains delay triggers, one of which is connected via the open contact of a pulsed traveling relay to the common power bus and through tO one inverter to the input bus and the other is connected to a common power bus through another inverter and the closing contact of the pulsed traveling relay, moreover, one delay trigger is connected to the push-pull register write bus, the control outputs of which are associated with the key elements of one and other signaling units, each of which contains Exit key element and a capacitor connected in series drive blocking oscillator, a trigger, which is connected through an amplifier 25 the signal PE le LIJ.

A disadvantage of the known decoder is that it allows the appearance of more permissive AEs.

The indications of the outdoor traffic light due to an accidental register failure.

The purpose of the invention is reliability.

The goal is achieved by the fact that each alarm unit is equipped with an inverter connected between an inverter and a key element connected in series by one capacitor and one resistor, the common connection point of which is connected via a diode to the information output of the register of another alarm unit and connected between the control output of the register and the inverter each signaling unit is connected in series by another capacitor and another resistor, the common connection point of which is connected to the common food bus.

The drawing shows the functional diagram of the numeric decoder. code

Claims (1)

The decoder closes the push-pull register, consisting of cells 1-4, to the reset outputs of which the driver of 5 pulses is connected, and to the control outputs b - signaling blocks 6.7. Each alarm unit includes serially connected one capacitor 8, one resistor 9, inverter 10, another capacitor 11, another resistor 12, switch 13, capacitor drive 14, blocking generator -15, trigger 16 amplifier 17 and signal relay 18, points the capacitor 11 and the resistor 12 are connected via a diode 19 to the common power supply bus / a connection point of the capacitor 8 and a resistor 9 through the diode 20 to the information output from the cell 3 registers, to the control output b of which the next signal unit 7 is connected Krom In addition, the decoder contains input buses 21 and 22, two inverters 23 and 24, closing 25 and opening 26 contacts of the transmitter relay, two delay 27.28 delays, the register contains the write bus 29. One of the delay flip-flops 27 has a control input d, a synchronization input e, a setup input zero f, a setup input unit q, outputs h and i. Another delay trigger 28 has control input k, synchronization input f. , the input of the installation of the unit m and the output of the item. The decoder works as follows. in the initial state in all cells of register 1-4 zeros are written, triggers 27 and 28 are units, bus 21 has a single potential, bus 22 has zero, capacitor 11 is charged, and the cover is connected to control output b of the register positive potential, and to resistor 12 - potential of the common power supply bus, capacitor 8 is discharged. In view of the presence of a resistor 12, the zero potential does not lead to the appearance at the output of the inverter 10. When the first code pulse arrives, the potentials of the buses 21 and 22 change their values, and at the output of the inverter 23, and, consequently, at the sync output e of the trigger 27, a voltage drop occurs from 0 to. If previously the opening contact 26 was closed, then the trigger 27 comes to the zero state, as its control input d is zero potential. The change of the potentials at the outputs i and h of the trigger 27 leads to the entry in the cell 1 register. When the potential at the control output b of the register is about 1 to C changes, the capacitor 11 is discharged through the resistor 12 to the input of the inverter 10, as a result of which the voltage on the circuit briefly decreases with the unit potential. This potential charges the capacitor 8 cher diode 20, provided that cell 3 of the register is not recorded 1 and there is a zero potential at its information output. After the zero potential is again set at the output of the inverter 10, the capacitor 8, via a resistor 9, negatively affects the key 13, closing it for a short time, thereby causing a charge on the capacitor in the accumulator 14. Opening the key 13 causes the blocking generator 15, receiving inverse power from the capacitor of the accumulator 14, generates short pulses with a high duty cycle. The pulses from the blocking generator 15 are fed to the counting input of the trigger 16, so that the latter produces oscillations of a rectangular shape. These oscillations are amplified and rectified by amplifier 17, which ensures the continuous operation of the signal relay 18. In the case of a false record i, the cell 3 of the register on its information output C has a single potential, as a result of which capacitor 8 is not charged, on its lining connected to the resistor 9, the negative potential does not occur :: and the key 13 is not momentarily closed. This leads to the fact that the capacitor of the accumulator 14 is not charged and the blocking generator 15 does not receive power, stops the generation of pulses. As a result, the signal relay 18 is turned off. After the termination of the first code pulse, the trigger 27 returns to the initial state (is written), as a result of which a record is written in the cell 2 of the register. When a long interval arrives, the driver 5, having a pulse input, generates a reset pulse, which drives cells 1–4 of the register to the initial state. The described decoder has an advantage over the well-known B, which eliminates the appearance of more permissive readings of the outdoor traffic lights due to accidental failures of the register, which consist in premature recording in the register cells. Claims A numeric code decoder containing delay triggers, one of which is connected via a break contact of a pulsed traveling relay to a common power bus and through one inverter to an input bus, and the other is connected to a common power bus of another inverter and a closing contact of a pulse traveling relay, one delay trigger is connected to the push-pull register write bus, the control outputs of which are associated with the key elements of one and the other signaling units, each of which contains connections data to the output of the key element and connected in series capacitor drive, blocking generator, trigger to which a signal relay is connected through an amplifier, characterized in that, in order to increase reliability, each alarm unit is equipped with an inverter connected between the inverter and the key element connected in series a capacitor and one resistor, the total connection point of which is through The diode is connected to the information output of the register of another signaling unit, and connected between the control output of the register and the inverter of each signaling unit, serially connected by another capacitor and another resistor, the common connection point of which is connected to the common power supply bus. Sources of information taken into account in the examination 0 1, USSR Copyright Certificate No. 652012, cl. B 61 L. 23/14, 1977.