SU1539972A1 - Pulse sequence generator - Google Patents

Abstract

The invention can be used as a master oscillator in automation and computing devices. The purpose of the invention is to increase the reliability of operation, which is achieved by introducing an element AND 19, the potential at the output of which blocks the triggers 2, 12 from false triggering, if a zero code is written to the register 17. If the zero code is recorded in register 5, then the trigger 12, which forms the output pulse sequence, is blocked by a clock input, the potential from the counter output 8 through the element OR 9. The device also contains a differentiating circuit 3, the element OR 4, the bus 6, setting the pulse duration code, block 7 of the elements OR, element 10, the driver 11 pulses, the bus 13 of the generator of the reference frequency, elements 14, 15, the output bus 16, the bus 18 setting the pause code. 1 il.

Description

The invention relates to a pulse technique and can be used as a master oscillator in automation devices and computer techniques.

The aim of the invention is to increase the reliability of

The drawing shows a functional diagram of a pulse train „

The pulse sequence generator contains bus 1 Start, trig; ger 2, differentiating circuit 3, element OR 4, register 5, bus 6 setting the pulse duration code, block 7 of elements OR, counter 8, element | OR 9 element AND 10, pulse generator 11, trigger 12, generator 13 of the reference frequency generator, elements 14 and 15. output bus 16, register 17, bus 18 specifying the pause code and element, element 19.

, Bus 1 Start with installation input in trigger 2

the trigger / direct output of which through differentiating text 3, the OR 4 element is connected to the information input input from the register 5, the information recording inputs of which are connected to the bus 6 to set the pulse readability code. The outputs of the register 5 are connected through the block 7 elements OR to the inputs of the installation of the counter 8, the outputs of which through the element OR 9 are connected to the first input of the element AND, 10, with the input of the driver 11 pulses, with the counting input of the trigger 12. The second input of the element AND

10 is connected to the bus 13 of the generator of the ground frequency. Shaper output

11 pulses are connected to the first inputs of the elements 14 and 15, the inverse output of the trigger 12 is connected to the second input of the element 16, the output of which is connected to the second input of the element 4 or 4 "forward output of the trigger 12 is connected to the second input of the element 15 and the output bus 16 The output element P

15 is connected to the read input of the register 179, the information write inputs of which are connected to the pause code setting bus 18. The outputs of the direct register code 17 are connected to the second inputs of the block 7 of the OR elements. The outputs of the inverse code of the register 17 through the element And 19 are connected to the inputs of the installation in O of the flip-flops 2 and 12, The output of the element And 10 is connected to the input of the subtraction of the song 8.

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five

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five

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five

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five

The registers 5 h 7 are identical and contain riggers with information recording inputs. The forward outputs of the flip-flops are connected to the first inputs of the And elements, the second inputs of which are combined and are the information readout input. The inverted outputs of the triggers are inverse outputs of the register 17, The outputs of the And elements are the direct outputs of the registers 5 to 7

The generator of impulse performance operates as follows.

Before starting the triggers 2 and 12s, registers 5 and 179, counter 8 is set to O. The zero code in counter 8 through the element NLP 9 blocks the transmission pulse from the frequency frequency from the first slot element 10 to the counter 80

Then the information of the co- and the duration of the IC is compressed; .., in the form of the rm, into the register 5 and the code ttnz: r impulse, r h gis c 17t 1o to the command icus: C 2 transitions tsr to the es / ation 1. At the direct exit 1rigpr 2, a high tial-dks ferment chain 3 chain appears;

PULSE FOG1 PVPT PULSE WITH “AND 1 Yvani e kotougg through STMM-y IGGI n nocfynae tg input: information from the 5S register 5S Information about the duration code and -tul.s comes through block 1 ev I.

INPUTS HF .P- 5 | Gog ° t ODYa tr G e 1bE

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AGREEMENT J vT-FBUJCi N G e1 and GRA 3, On 5-: „,. /e-te G.TI 9 appears BUr, -, l. GO G-, CH Ј, 9 T OTOR:

Pasoerjaei) OS .-. GO1K, G, E / L-G M Lulsoz Z11 A Ponno - sg-G-EDTEG T 10 to the subtractive i.rei-iC - i S and translate trigger 12 z'r -; K - those condition. On exit but; M - the front of the output-pulse is formed. The high potential at the direct output of the trigger 12 prepares the element AND 15 for the passage of impuls. The pulses of the reference frequency go through the element 10 to the subtractive input of the counter 8, subtracting the contents of it one by one. When the counting input of the counter 8 arrives N, f pulses of the reference frequency, the output of the element OR 9 appears at a logic zero level, which closes the element 10 and blocks the passage of the pulses of the reference frequency cha of the subtracting input of the counter 8,

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The level of logical zero from the output of the element OR 9 also enters the input of the driver 11 pulses, which forms a pulse arriving at the first inputs of the elements 14 and 15. And the element 14 is closed at the second input by a low level signal from the inverse output of the trigger 12s and element 15 also open the high level of the signal from the direct output of the trigger 12, the pulse from the output of the driver of 11 pulses through the element 15 goes to the read input of the register 17, from which it reads the direct code. The direct code M2 of the output of the register 17 goes through block 7 lementov adjusting inputs to OR 8 May transfer counter triggers the counter 8 in a single state according to the code dlitelnostipau- i sbiN-j. The inverse code N g from the output of the register 17 goes to the inputs of the And 19 element. If the pause code W2 is not zero, then J at the output of the And 19 element is a low signal level. Since the NI code is not zero, a high level appears at the output of the OR 9 element. The signal of the logical unit from the output of the OR 9 element allows the passage of the pulses of the reference frequency through the EI element to the subtracting input of the counter 8 and 5 to the counting input of the trigger 12, returns it to its original state. At the direct output of flip-flop 12, the signal is a logical zero 5 at the inverse of a signal of a logical unit. When the trigger 12 is brought to the initial state, the output pulse is formed at the direct output. The signal of the logical unit from the inverse output prepares the element. And 14 for the passage of pulses. The pulses of the reference frequency generator

arrive through the element AND 10 on bb reading the input of counter 8, subtracting from it the contents of one. When to the subtracting input of counter 8, the output of NJ pulses of the reference frequency, the output of the element OR 9 appears at the level of logical zero, which closes the element And 10 and blocks the passage of pulses of the reference frequency to the subtracting input of counter 8, the level of logical zero element OR 9 is fed to the input of the imager 11 impuls, which generates pulses arriving at the first inputs of the elements And 14 and 15. And the element 15 is closed by a logic level

Q 20 25 30

P

35

45

five

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which zero, coming from the direct output of the trigger 12, the element AND 1A is open, the pulse from the output of the driver 1 1 pulses goes through the element AND 14, the element OR 4 to the read input of the register 5. Informing the pulse duration code from the output of the register 5 through the block 7 elements OR arrives at the installation inputs of the counter 8. At the output of the element OR 9, there appears a level of a logical unit that translates trigger 12 into a single state and allows the reference frequency to pass through the AND 10 element to the subtracting input of counter 8. If the numbers N1 and N is not changed, the output bus 16 of the generator periodically pulses are N code and a space between them, as determined by Nt code. If the numbers N. and N change, then pulses of duration N1 and pause N2 appear on the generator output 16, defined by the new code.

If the Islam code N. is equal to Kull, then there will be no output pulse at the output of the generator, since the read pulse received by the Start command via trigger 23 differentiating chain 3, the OR 4 element at the read input of register 5, records the zero code in counter 8 through block 7 elements OR. Since the presence of a zero code in the counter 8 determines a low level at the output of element 9, the pulse of the reference frequency cannot pass through the element 10 to the subtractive input of the counter, trigger 12 remains in the initial state. A pulse generator with controlled frequency will not fail. For normal operation, it is necessary to set the control trigger 2 to its initial state.

Claims (1)

If the code of the number N is not equal to 05, but the code of the code of the number fli, then the inverse outputs of register 17 are 1, therefore, the output of the AND 19 element will also be 1, which blocks triggers 2 and 12. On the output bus 16 no impulses are generated, therefore, the generator does not work properly - the “formula invented Pulse train generator, containing the first trigger, the first register, the counter, the input of which is connected to the output of the first element I, the first input of which is connected to the reference frequency generator bus, the second trigger, the direct output of which is connected to the first input of the second element I, the output of which is connected to the input of the reference The second register, the inverse input of the second trigger, is connected to the first input of the third element AND, the first element OR, the Start bus, characterized in that, in order to increase the reliability of operation, a differential circuit is introduced into it, the second element OR, the driver pulses, a block of OR elements, a fourth AND element, and the Start bus is connected to the preset input of the first trigger, whose direct output through the differentiating circuit is connected to the first input of the second five 0 the OR element, the second input of which is connected to the output of the third AND element, the output of the second OR element is connected to the read input of the first register, the bit outputs of which are connected to the first inputs of the OR element block whose outputs are connected to the counter installation inputs, the outputs of which through the first element OR is connected to the clock input of the second trigger, the second input of the first element AND and the input of the pulse shaper s whose output is connected to the second inputs of the second and third elements AND, the outputs of the direct code the second register is connected to the second inputs of the OR block; the outputs of the inverse code of the second register are connected through the fourth element I to the installation inputs of the first and second triggers.