SU743211A1 - Binary signal regenerator - Google Patents

Description

The invention relates to radio engineering and can be used in discrete information transmission equipment. A binary signal regenerator is known, containing a block of buffer memory elements, two input distributors for recording and reading information, specifying a generator connected to the input of a synchronization unit, and an output trigger | However, such a regenerator does not provide high accuracy of regeneration. The purpose of the invention is to improve the accuracy of regeneration. For this purpose, an asynchronous receiver, an OR element, a block of recording elements, are inserted into the regenerator of binary signals, the contents of a block of buffer memory elements, two combined distributor inputs for recording and reading information, specifying a generator connected to the input of a synchronization unit, and an output trigger. a block of read elements, an OR block, a key and a series-connected addition unit, a subtraction unit, a distributor and a switch; one output of the switch is connected via the first counter to the input of the addition unit, second The second output is connected via the second counter to another input of the subtractor, and the third output is connected to the other inputs of the first and second counters, and the outputs of the asynchronous receiver are connected to the inputs of the block of recording elements, and through the OR element to another input of the switch and another input of the synchronization block, the first output of which is connected to another input of the addition unit, and the second output is connected to the input of the key, the output of which is connected to the control input of the first distributor for recording and reading information:: bit outputs connected to the inputs of the readout block, whose outputs through the OR block of inputs are connected to the inputs of the output trigger, while the fourth output of the switch is connected to the control input of the second distributor for recording and reading information, the bit cells of which through the serially connected block of recording elements and the block buffer elements

na mt; connected to other inputs of a block of read elements, and the outputs of the block of memory elements are connected respectively to other inputs of the block of record elements, while the corresponding bit output of the second distributor for recording and reading information is connected to another input of the key, and the output of the master oscillator is connected to another input an asynchronous receiver, to the third input of the key and other inputs of the first and second distributors for recording and reading information, a signal was set to zero,

The drawing shows the structural electrical circuit of the proposed regenerator.

The binary signal regenerator contains a block of 1 elements of buffer memory, valves 2. and 3 for recording and reading information, a master oscillator 4, a block 5 of synchronization, an output trigger 6, an asynchronous receiver 7, an element OR 8, a block 9 of elements of a record, a block of 10 elements reading, block 11 of elements OR, key 12, block 13 of addition, block 14 of subtraction, distributor 15, switch 16, counters 17 and 18.

The device works in the following way.

The binary information signal is fed to the input of the asynchronous receiver 7, at the outputs of which, depending on the input signal, pulses are formed, which correspond to the limits (alternating signs) of elementary parcels. Impulses corresponding to positive sign changes (About binary information goes into); removed from one input, the pulses of negative change sign (goes to O) - from another output. The asynchronous receiver 7 eliminates fragmentation of the parcels and operates according to the discrete principle, for which a sampling frequency signal from the master oscillator 4 is supplied to one of its inputs. In this case, no special synchronizing pulses are required for the asynchronous receiver 7 to operate. The pulses of positive and negative alternating signs in the input signal are fed to the inputs of block 9 of the recording elements. From the output of the synchronization unit 5, through the addition units 13 and subtraction 14, the pulse signal is fed to the input of the distributor 15 with a frequency exceeding 4 times.

Frequency frequency

designed for 4 outputs and simultaneously performs the function of a conventional counter, therefore the signal from the 4th output of the distributor 15 has a clock frequency and controls the operation of the distributor 2.

In the absence of phase fluctuations in the input signal, the pulse frequency and the phase of the signal from the output of the distributor 15 coincides with the clock frequency fg. When phase fluctuations, especially correlated, occur, the input signal is shifted in phase to the side, while the phase of the recording signal without taking special measures remains unchanged due to the high inertia of sync 5, If you record information in unit 1 with constant clock frequency, then there are errors when the amplitude of the oscillations, together with the noise fluctuations of the phase of the boundaries of the parcels, exceed half the duration of the parcels.

In order for the error elements to fail to write to block 1, the recording signal phase should repeat the phase sweeps of the input signal, i.e. In accordance with the phase of the input signal, the phase of the control pulses of the distributor output 15 must change.

In the absence of oscillations of the signal at the input of the regenerator, the phase position of the output boundaries of the parcels corresponds to the middle of the clock period of the pulse sequence from the output of the distributor 15. The actual noise fluctuations of the boundaries of the parcels are usually small and mostly in the interval from + 1 / 4Со {where m: parcels).

The swing of the input signal phase leads to the fact that, starting from a certain moment in time, the phase of the boundary of the elementary parcel acquires a regular displacement, which, exceeding the value of ± 1 / 4tQ, begins to coincide in time either with (-1 / 4To) or with + 1/4 tgd) states of the distributor 15. If there are three such matches, then the pulses are added or subtracted at the input of the distributor 15.

This, in turn, leads to a change in the phase of the pulses (recording signal) by +1/4 (or -1/4) period of the clock frequency fo and provides tracking of the phase oscillation of the input signal, since after such adjustment of the phase of the recording signal the phase position the subsequent boundaries of the elementary parcels are already again about the middle of the clock period of the gating pulses. If the input signal continues to swing and then AND exceeds + 1 / 2To (or, another subtraction (or addition) occurs, which leads to a change in the phase of the recording signal by 1/2 clock period.

At weakening of a swing (change of a phase towards a normal position) there is an inverse adjustment - by adding and subtracting pulses the initial normal

phase drove the record. The likelihood of displacement of the parcel of the parcel beyond ± 1/41 three times a day is due to the usual marginal distortion is negligible

Signals to the input of each of the counters 17 and 18 comes from vyhrda com-. a mutator 16, to the inputs of which pulses are given alternating sign in the input signal and the potentials from the output of the distributor 15,

The pulses from the outputs of the counters 17 and 18 are fed to the inputs of the blocks for the addition of pressure 13 and subtraction 14,

The transfer of the recording process from one cell of a block of 1 elements to another occurs at the time of the occurrence of the next gating pulse (recording signal). Therefore, the initial recording of information into each subsequent cell is made depending on what is written in the previous cell, If in the previous cell was recorded (or O), then 1 (or, respectively, O) is entered into the subsequent one. This process is carried out at the moments of switching the cells of the 1 unit of elements.

If, during the new clock interval, no binary information is exchanged, then the cell state of unit 1 does not change. If the sign of the parcel changes, the state of the next cell automatically changes,

The sequence of reading and switching from one cell of the block 1 of elements to another is provided by the valve 3,

Reading the information in the regenerator lags the record by time, different n / 2i: o, where n is the number of cells of the block of elements (in our case, p 4). To prevent overflow of the block of elements, the maximum departure of the input signal in this case is + n / 2C. The delay of the read cycle with respect to the write cycle for a time is as follows.

The beginning of the recording cycle can be considered. the moment of occurrence of the trailing edge of the first pulse arriving at the input of the distributor 2. To ensure the read cycle lags 2 C, it must start at the moment of the emergence of the trailing edge of the third pulse which coincides with the trailing edge of the pulse at the second output of the distributor 2, therefore the signal from this output through the key 12 opens the clock to the input of the distributor 3, the key 12 is closed by the impulse installation O, which is formed at the moment of switching on the equipment with the same impulse at the start

the operation of the regenerator is carried out by setting zero of the valves 2 and 3.

Thus, in the binary signal regenerator, the likelihood of false reception of information is reduced, and the high cyclic stability of clock synchronization is ensured.

Claims (1)

Invention Formula A binary signal regenerator containing a block of buffer memory elements, two input distributor for recording and reading information, a master oscillator connected to the input of the synchronization unit, and an output trigger, characterized in that, in order to improve the regeneration accuracy, an asynchronous receiver is inserted, an OR element, a block of recording elements, a block of reading elements, a block of OR elements, a key and a series-connected addition block, a subtraction block, a distributor and a switch; one output of the switch through the switch The second counter is connected to the input of the addition unit, the second output is connected via the second counter to another input of the subtraction unit, and the third output is connected to the other inputs of the first and second counters, and the outputs of the asynchronous receiver are connected to the inputs of the recording element block, and through the OR element to another the switch input and the other input of the synchronization unit, the first output of which is connected to the shuzhny input of the addition unit, and the second output is connected to the input of the key, the output of which is connected to the control input of the first distributor for recording and reading information, the bit outputs of which are connected to the inputs of the block of read elements, the outputs of which through the block of elements OR are connected to the inputs of the output trigger, while the fourth output of the switch is connected to the control input of the second distributor for writing and reading information, bit outputs which, through series-connected block of recording elements and block of buffer memory elements, are connected to other inputs of the block of reading elements, with the outputs of the block of memory elements connected respectively, to the other inputs of the block of recording elements, while the corresponding bit output of the second distributor for recording and reading information is connected to another key input, and the output of the master oscillator is connected to another input I of the asynchronous receiver;