SU777870A1 - Device for receiving address signals in asynchronous pulse communication systems - Google Patents

Description

one

The invention relates to telecommunications and can be applied in radio telemetry systems with code division channels (messages).

A device for receiving signals in asynchronous-pulse communication systems is known, comprising a pulse reception unit whose output is connected to the input of the shift register, whose outputs are connected to the first key inputs through the decoder, the second inputs and outputs of which are connected respectively to the output of the pulse receiving unit. and receiver information inputs 1.

However, the known device has an increased likelihood of detecting a spurious signal caused by a combination of the address code of other messages (channels).

The purpose of the invention is to improve the noise immunity.

For this, the device for receiving address signals in asynchronous-pulse communication systems contains a pulse reception unit whose output is connected to the input of the shift register, the outputs of which are connected to the first key inputs through the decoder, the second inputs and outputs of which are connected respectively to the output of the block reception of pulse signals and inputs of receivers of information.

introduced in series connected threshold block and logic block, the outputs of which are connected to the additional inputs of the shift register, while the outputs

5 decoder connected to the inputs of the threshold unit and the corresponding inputs of the logic unit.

The drawing shows a structural electrical circuit of the proposed device.

10 A device for receiving address signals comprises a block 1 for receiving pulse signals, a shift register 2, a decoder 3, keys 4, information receivers 5, a logic block 6, a threshold block 7.

15 The device operates as follows.

From block 1 of the receiver of pulse signals, the codes of the addresses of the transmitted messages go to shift register 2, having taps corresponding to the address codes with a passive pause.

The decoder 3 performs the allocation of addresses with the full or partial coincidence of the pulse signals at certain taps of the shift register 2 and opens

corresponding key 4 for entry

measurement code in the receiver 5 information.

Simultaneously selectable address with

the output of the decoder 3 is supplied to a logical block 6 of address codes, which generates signals intended to erase the pulses corresponding to the code of the selected address in shift register 2 using the elements NO.

As a result, the pulses of the code of the selected address in combination with the received pulses of the subsequent address code cannot form a false address of the message, which distinguishes the proposed device from the prototype.

It should be noted that although the transmission of the address codes of different messages is chosen so that they have certain intervals in between pulses that are peculiar only to them, however, a false address code can be formed while simultaneously receiving the address codes of several messages. In this case, the allocation of a false address may lead to the non-allocation of subsequent transmitted addresses. Therefore, to protect the device from spurious address allocation while simultaneously receiving address codes, a threshold unit 7 is connected to the outputs of the decoder 3, which is triggered by simultaneous allocation (K + 1) or more addresses and a blocking logic unit 6, and, if necessary, also a receiver 5 of information.

If at the same time the ensemble of address codes is chosen so that the simultaneous transmission of K or fewer addresses does not constitute a different address code or the number of simultaneously transmitted addresses is limited to the transmission of K, then at reception the threshold unit 7 will detect a false address allocation situation when the NIR is triggered.

Thus, the proposed device can significantly reduce the likelihood of allocating a false address caused by a combination of address codes of other messages, both in the case of the simultaneous reception of address codes of several messages, and when receiving subsequent message address codes.

Claims (1)

Invention Formula An apparatus for receiving address signals in asynchronous-pulse communication systems comprising a pulse reception unit whose output is connected to the input of the shift register, whose outputs are connected to the first key inputs through the decoder, the second inputs and outputs of which are connected respectively to the output of the pulse receiving unit and inputs of information receivers, characterized in that, in order to increase the noise immunity, a series-connected threshold block and a logic block are introduced, the outputs of which are connected to g Additional inputs of the shift register, while the outputs of the decoder are connected to the inputs of the threshold unit and the corresponding inputs of the logic unit. Sources of information taken into account in the examination 1. I. Agadlanov and others. “Fundamentals of radio telemetry, Moscow, USSR Ministry of Defense, 1971, p. 148-151 (prototype).