SU752373A1 - Exponential function generator - Google Patents

Description

The invention relates to the field of analog computing.

A device is known that can be used to obtain a function of the form exp (+ At / (f), containing a key element, the input of which is connected to the output of the first integrator and the output of the zero organ, and the output is connected to the input of the second integrator, and a conversion unit through which the output is zero -organ connected to the input of the first integrator £ 1].

However, the conversion time with acceptable accuracy is large, in addition, this device does not allow to obtain a function with a fractional exponent. _J5

A device is also known based on the discharge of a capacitor C via an R circuit in which the original function, for example, time At, is converted to a voltage across the capacitor £ 2]. _m

However, this device does not allow obtaining a function of the form exp (+ A t / ΐ) with a positive exponent.

The closest in technical essence to the invention is a functional converter containing a subtraction unit, the inputs of which are connected to the source c to the pulse generator, and an additional controlled key through which the RC resistor is connected to the zero potential bus. Moreover, the control input of the additional key is connected to the output of the subtraction unit, and the control input of the first key is connected to the output of the pulse generator £ 3].

The disadvantages of this device are the small dynamic range of the exponential function, the inability to obtain exponential real exponents.

The purpose of the invention is the increase in the dynamic range and the possibility of obtaining an exponential function with real exponents.

This goal is achieved by the fact that in an exponential functional converter containing an integrating RC circuit, a pulse former block, the inputs of which are connected to the first and second signal source, the first key is connected in series with the register of the integrating RC circuit, and the second key is connected between a capacitor of an integrating RC circuit and a reference voltage source, the control inputs of the keys are connected to the corresponding outputs of the pulse shaper block, an additional logic block, an integrator, an element are introduced Comparison, buffer cascade, OR element, inverter, current generator, moreover, the inputs of the logic block are connected to the third and fourth outputs of the pulse shaper block, the first output of the logic block is connected to the control input of the current generator, output. which is connected to the output of the integrating PC circuit, the second output of the logic unit is connected to the discharge input of the integrator, the input of which is connected to the first input of the first comparison element and through the buffer cascade to the integrating PC circuit, the output of the integrator is connected to the first input of the second element ^f - comparison, the second input of which is connected through the inverter to the reference voltage source, and the second input of the first comparison element is connected to the zero potential bus, the control inputs of the first and second comparison elements are connected to the second and first outputs of the logic block, respectively, and the outputs of the comparison elements are connected via the OR element to the output of the converter, the third input of the logic block and the third input of the pulse shaper block are connected to the converter start bus.

The logic block is made up of two triggers, the first inputs of the triggers are the first input of the logical block, the second inputs of the first and second triggers are the second input of the logical block, the third inputs are the third ¹ input of the logical block, the inverse output of the first and direct output of the second triggers are respectively the first and second logic block output.

The drawing shows a schematic diagram of a converter.

The converter contains the first and second signal sources 1 and 2, a pulse shaper unit 3, triggers 4,5, 6 and 7, an element. Exclusive OR 8, element 9 AND, respectively, the first and second keys 1O and 11, inverter 12, the bit key of the integrator 13, buffer

17, first, comparison, block 21. as follows

752373 4 stage 14, integrating RC — circuit 15, current generator 16, inverter and second elements 18 and 19 element OR 20, logical The converter operates in a manner.

By the Start pulse, all the triggers of the pulse former and the logic block are set to zero. The first key is open, the second key is closed and the capacitor of the integrating RC circuit will be charged to voltage E &. According to the first impulse from the signal sources (no matter which), the second key is opened using the pulse shaper block and the first key is closed. The voltage across the capacitor is then changed exponentially.

^U C ₁ ^{= E} o ^ex p (- ^t / ' ^t id)

According to the second pulse from the signal sources, the first switch is opened using the pulse shaper unit, and the voltage on the capacitor will be [- if 2 or u _c , = Е _о exp [- (b _g 1 ₂ ) / g] if ₍₃₎

Ego voltage is converted into a duration T _ol as follows. If t 2> 11, then using the logic block the integrator bit is opened, and the voltage at its output changes according to the law ^ Output int ~ 2 ^С 2 (4)

After time T _P p from the start of integration, the second element of comparison will work

Uc, _t - _E _o exp [- (t ₂ -t,) /?] Tnp ^₽ 2 ^C 2 ^PR_ ° ~ ^K 2 ^C 2 and exp,) / 1] = p / T? ₂ C2

Thus, for 1 ₂ > t j. an exponential converter with a positive exponent is obtained.

If t · 2/11 ', then via the logic block includes a current generator, wherein the integrating capacitor is recharged PC- chain linearly, and the time of overcharge of ₀₁ U equal to zero ^{IN' T} P _Uc, C, E ₀ C. _{Γ / ί,,} е «р [-“ Ч _г ) / -!] - Т _pr З / Е _<> с ₁ · ₍₆₎ (5) functions with real exponents, logic block, integrator, comparison elements are additionally introduced , buffer cascade, OR element, inverter, 5 current generator, and the inputs of the logic block are connected to the third and fourth outputs of the pulse shaper block, the first output is logical of the second block is connected to the control input of the current generator, the output of which is connected to the output of the integrating PC circuit, the second output of the logic block is connected to the discharge input of the integrator, the input of which is connected to the first input of the first comparison element and through the buffer cascade to the integrating PC circuit, the output the integrator is connected to the first input of the second comparison element, the second input of which is connected through the inverter to the reference voltage source, and the second input of the first comparison element is connected to the zero potential bus, the control inputs of the first and second comparison elements are connected respectively to the second and first outputs of the logic unit, and the outputs of the comparison elements through the OR element are connected to the output of the converter, the third input of the logic block and the third input of the pulse shaper block are connected to the Start bus of the converter.

2. Converter yo π. 1, which entails that the logic block is executed on two triggers, the first inputs of the triggers are the first input of the logical block, the second inputs of the first and second triggers are the second, the input of the logical block, the third inputs are the third input of the logical block, inverse output the first and direct outputs of the second triggers are respectively the first and second outputs of the logical block.

Sources of information taken into account during the examination

1. USSR copyright certificate No. 393749, class Q About C 7/20, 1971.

2. USSR author's certificate No. 444207, cl. G 05 Q 7/24, 1972.

3. USSR copyright certificate No. 304575, cl. Q 06 G 7/24, 1970 (prototype).

It is possible to choose a discharge current of such a magnitude that / E _O C | ⁼ 1 · / R 2 С2> (γ) then the proportionality coefficient at Т _П р in expressions (5) and (6) will be the same.

In the second case, we got an exponential converter with a negative exponent. The conversion time (Т _П р) in the first and in the second case is determined by the dynamic range and the accuracy of the representation of the function exp (δ представления /?).

So, if we take a minimum duration of 15, easily measured by modern devices with an accuracy of 1% per 1 μs, then with a dynamic range of representation of the function e * -4 ^{4, the} maximum conversion time will be 10 ms, 20 while the exponent will vary from - 4.6 to +4.6.

Thus, in the proposed exponential functional converter, it was possible to expand the dynamic range of the representation of the ё * function by tens of times, in addition, the proposed converter allows you to obtain an exponential function with a positive and negative exponent without 30 manual switching and without significant complication of the circuit, which extends the functionality of the converter .

Claims (3)

1. USSR author's certificate number 393749, cl. On q 7/20, 1971. 2. Avto.orskoe certificate of the USSR No. 444207, cl. G O5 Q 7/24, 1972. 3. USSR author's certificate number 304575, cl. q 06 G 7/24, 1970 (prototype). functions with valid exponents, additional logic block, integrator, comparison elements, buffer cascade, OR element, inverter, current generator, the logic block inputs are connected to the third and fourth outputs of the pulse driver unit, the first logic code block is connected to the control unit. the input of the current generator, the output of which is connected to the output of the integrating RC circuit, the second output of the logic unit is connected to the bit input of the integrator, the input of which is connected to the first input of the first the comparison element and through the buffer stage to the integrating RS-41epi, the integrator output is connected to the first input of the second comparison element, the second input of which is connected via an inverter to the reference voltage source, and the second input of the first comparison element is connected to the zero potential bus, control inputs the first and second elements of the comparison are connected respectively to the second and nepBON-iy logic codes of the logical block, and the outputs of the comparison elements through the OR element are connected to the output of the converter, the third input is logical one block and the third input of the pulse shaper block comp | sheny with bus Start transducer. 2. The converter yo p. 1, which is based on the fact that the logic block is executed on two triggers, the first inputs of the triggers are the first input of the logic block, the second inputs of the first and second triggers are the second, the input of the logic block, the third the input is the third input of the logic unit, the inverse output of the first and the direct output of the second flip-flops are respectively