SU721907A1 - Pulse shaper - Google Patents

Description

(54) PULSE FORMER

I

The invention relates to the field of computing and can be used in digital computing and control devices.

Known pulse shapers containing elements OR NOT, inverter, trigger 1.

The disadvantages of the known pulse shapers are the complexity of the circuit and the inability to generate pulses along the leading and trailing edges of the input pulse, which exceed its duration.

The closest to the technical essence of the invention is a pulse shaper on the front and rear edges of the input pulse, containing the first inverter, the input of which is connected to the first input of the first element And, and the output to the first input of the second element And, the second input of which is connected to the output of the trigger, and the output is with the first input of the OR element, a delay device, the output of which is connected to one input of the trigger 2.

The disadvantage of such a pulse former is the impossibility of generating pulses along the leading and trailing edges of the input pulse, exceeding it in duration.

The aim of the invention is to improve the functionality of the pulse former.

The goal is achieved by the fact that

into the pulse shaper containing

first inverter whose input is connected

with the first input of the first element I, and the output with the first input of the second element I, the second input of which is connected to the output of the trigger, and the output to the first input of the OR element, the delay device whose output is connected to the input of the trigger, the second inverter and the third Element I.

5 Moreover, the input of the first inverter is connected to the input of the delay device, the output of which is connected to the input of the second inverter and to the first input of the third element AND, the second input of the last is connected to the output of the first inverter, and the output to the second input of the OR element, the output of the second inverter is connected to the second the input of the first element And, the output of which is connected to the second input of the trigger.

FIG. 1 shows a functional diagram of a pulse former; in fig. 2 is a temporary chart of his work.

The output 1 of the pulse shaper is connected to the inputs of the inverter 2 and the delay device 3, the output of which is connected to the input of the inverter 4. Element 5 is connected to the input of the pulse shaper and the input of the delay device and input 7 to the output of the inverter 4. Trigger 8 input 9 connected to the output element And 5, and input 10 - with the output of the delay device and the input of the inverter 4. Element 11 And input 12 is connected to the output of the inverter 2, and input 13 to the output of the trigger 8 and to the output 14 of the pulse shaper. Element And 15 input 16 is connected to the output of the device 3 delays, and the input

17- with the output of the inverter 2. Element OR

18 is connected by input 19 to the output of the element 11, input 20 to the output of the element 15, and output to the output 21 of the pulse former.

The pulse shaper operates as follows.

In the initial state, after a reset pulse is applied, low voltage levels are set at the outputs 14 and 21 of the pulse shaper.

Consider the case when a pulse of positive polarity arrives at the input 1 of the pulse generator, the duration of which is less than the delay time ts installed on the delay device 3 (Fig. 2a).

The leading edge of the pulse from the pulse driver input goes to the input of the delay device and to input 6 of element 5. And element 5 opens, since at its input 7 (Fig. 26) there is a high voltage level. The leading edge of the pulse from the output of the element And 5 is fed to the input 9 of the trigger 8 and switches it to one state. At the output of the pulse shaper 14, the leading edge of a high voltage level is formed (Fig. 2b). The inverted input pulse from the output of the inverter 2 is fed to the input 12 of the element 11 and 11, to the input 17 of the element 15 and prohibits the passage of a pulse of positive polarity to the element OR 18 (Fig. 2d).

On the trailing edge of the input pulse, AND 11 and OR 18 elements open. At the output of the pulse shaper, a high voltage front edge is formed (Fig. 2e).

The leading edge of the input pulse, having passed through the delay device 3, is fed to the input 10 of the flip-flop 8 (Fig. 2e), to the input of the inverter 4, to the input 16 of the And 15 element. The flip-flop 8 switches to the zero state. At the output 14 of the pulse former, the back front of the output pulse is formed.

pulse (Fig. 2c). At this time, element 15 is opened. A delayed input pulse passes at its output and is fed to the input 20 of the element OR 18, where it maintains a high voltage level at the output of the pulse generator 21. The trailing edge of the delayed input pulse forms the trailing edge of the pulse at the output of the pulse former (Fig. D to e).

Thus, at the outputs 14 and 21 of the pulse former, pulses are received in the formed along the leading and trailing edges of the input pulse and exceeding it in duration.

Consider the cases when a pulse of positive polarity arrives at the input 1 of the pulse generator, the duration of which exceeds the delay time t set on the delay device 3 (Fig. 2a).

The formation of the front and rear edges of the pulse at the output 14 of the pulse shaper on the leading edge of the input pulse occurs in the same way as in the previous case. When trigger 8 is switched to the zero state to prevent a high level of input voltage from affecting its input 9, a pulse from the output of the delay device is fed through inverter 4 to input 7 of element 5 and prohibits it (Fig. 2e).

The formation of the leading and trailing edges of the pulse at the output 21 of the pulse shaper along the trailing edge of the input pulse is performed by AND 15 and OR 18 elements (Fig. 2 (3)).

Thus, adjusting the delay time can be obtained at the outputs 14 and 21

 pulse shaper pulses of a given duration along the leading and trailing edges of the input pulse of any duration.

The use of the invention allows

0 to extend the functionality of the pulse former along the front and rear edges of the input pulse, to unify pulse formers of a similar type while simultaneously expanding their functionality when designing computing devices based on a potential system of elements.

For example, when using a pulse former to form pulses on the leading and trailing edges of an input pulse, which are shorter in duration, the functionality of the pulse former can be extended by the ability to detect interference pulses arriving at its input,

the duration of which is less than the delay time, and prevent their effect on subsequent circuit nodes. To do this, it is necessary to connect a two-input element I to the outputs of the imaging device, the output signal from which can be used to detect the presence of interference pulses and to prohibit the effect of interference on subsequent circuit nodes. Connecting to the output of the pulse generator element OR will allow you to remove from the output pulses of double frequency.

Claims (2)

1. USSR author's certificate number 400987, cl. H 03 K 5/153, 1971. 2. USSR author's certificate number 455468, cl. H 03 K 5/04, 1972. P / a § 8 andI g - d e -f-ts