SU566378A1 - Apparatus for synchronization of discrete phase-wise self-tuning - Google Patents

Description

(54). DEVELOPMENT OF SYNCHRONIZATION OF DISCRETE PHASE OF AUTOMOTE

to the input of the OR element, and the correction inputs, the exclusion of pulses and the addition of pulses, are given to the second inputs of the memory trigger of the second and third additional elements H, respectively.

The drawing shows a structural electrical circuit of the proposed device.

The device contains a series-connected input signal regenerator 1, an inverter 2, the first element AND 3 and the element OR 4; To the second input of the first element I 3 is connected one of the control trigger 5 outputs, between the other output and the first input of which are connected the serially connected second element 6, the second input of which is connected to the input of the regenerator 1 of the input signals Shaper of the reset signal 7. Input of the regenerator 1 of the input signal through sequentially connected the first additional element AND 8 and the optional shaper of shuhles g is connected to the first input of memory trigger 1О, the output of which is connected to the second input of the first o | Additional element AND 8. The output of the additional pulse generator 9 is connected through the additional inverter 11 to the first inputs of the second i2 and third 13 additional AND components, whose outputs are connected to the second input of the control trigger 5 and the second input of the OR 4 element, and the second the inputs of the memory trigger 10, the second 12, and the third 13

correction signals, pulse exclusion and pulse addition.

The device works as follows. If there is no correction pulse, then the pulse impulse arrives at the device input and through the narrow impedance regenerator 1 tied to the leading edge of the input pulses, the inverter 2, the first element And 3 and the element OR 4 enters the device output.

If the correction pulse acts on the memory trigger input 10 and a pulse suppression signal is received, the correction pulse sets the resolution for the input pulses | by moving the memory trigger 10. through the first additional element And 8, which are then converted into narrow pulses, tied to the trailing edge of the input pulses with the help of a shaping device 9.

Setting the trigger of memory 10 to the initial state occurs with the next pulse input. The impulse from the output of the impulsor1 .-, owl 9 driver, through the inverter 11, also goes to the inputs of the elements 12,

13. The pulse through the open element And 12 sets the trigger control 5 to the state in which the element And 8 is open and the element And 3 is closed. This condition lasts until the end of the next input. pulse and thus this pulse will be knocked out of the series. The pulse shaper 7 outputs a narrow pulse tied to the end of the input pulse, and control trigger 5 is reset, in which the input pulses pass through the AND 3 element.

If the correction pulse acts on the input of the memory trigger 10 and a control signal is received by adding a pulse, then the operation of the memory trigger 10, element 8, pulse generator 9, inverter 11 is similar to that described above. The pulse from the inverter 11 through the open element And 13 and through the element OR 4 is fed to the output of the device, and between the two output pulses another pulse is added, formed on the trailing edge of the first input pulse. .

The proposed device will reduce the time of entry into synchronism.

Claims (1)

1. USSR author's certificate No. 175082 MKI 2N 04 L 7/04, 1963. LL