SU710008A1 - Follow-up filter for processing signal with suppressed carrier frequency, phase of which is manipulated by the law of binary pseudorandom train - Google Patents

Description

(54) S.PEDING FILTER FOR TREATMENT OF A SIGNAL WITH A PRESSED LOSS, THE PHASE OF WHICH A MANIPULOUBROBAN IS ACCORDING TO THE LAW OF A BINARY ALTERNATIVE SEQUENCE

coherent discriminator delay tracking circuit 2, having two identical channels containing serially connected multipliers 12, narrowband IFA 13 and amplitude detectors 14 connected to the inputs of the adder 15, the output of which is connected to the filter of the lower part 16 connected to the controlled clock generator 17, output This generator is connected to the shift register 18, consisting of. (n + 1) triggers.

The output of the nth trigger of the shift register 18 is connected to the phase demodulator 5, and the outputs of the (n + 1) -th and (n-l) -ro Triggers are connected to the inputs of the multipliers 12

The device works as follows. A broadband signal with phase shift keying according to the binary pseudo-random sequence is fed to the input of the mixer 3 of the following filter. At the output of the phase demodulator 5, a signal is compressed across the spectrum, which is filtered by narrowband OFAC b and monitored by the FAP 1 circuit in a conventional manner.

In multiplier 12, the broadband signal is multiplied by two modulating functions shifted by 2to, where% is the duration of one discrete sequence. If one of the sequences coincides with the modulating function of the signal to a greater extent than the other, then in that of the multipliers 12 to which this sequence arrives, a more complete recovery of the carrier will occur (signal compression) and the output of the corresponding amplitude detector 14 which will exceed the voltage at the output of the second channel detector. The voltage difference from the output of the amplitude detectors 14 adjusts the controlled clock generator 17. The delay of the sequence, removed from the n-th trigger of the shift register

18, with respect to the transmitter radiated, can be used to measure the range, and the frequency of the signal from the output of the FAP 1 circuit to measure the speed.

- We propose a following filter for incoherent signal processing, the phase of which is manipulated according to the binary pseudo-random sequence, a simpler design and allows you to speed up the establishment of the synchronization mode of the delay tracking circuit that outputs the demodulation signal to the PLL for entering it into the frequency tracking mode .

Claims (1)

Invention Formula The following carrier-suppressed signal processing filter of which is manipulated according to the law of a binary pseudo-random sequence consisting of a phase locked loop (PLL) containing a mixer / one input of which receives a received signal and another output of a circuit connected to the mixer consisting of a phase demodulator, a phase detector with a reference local oscillator and controlled generator and connected with a PLL circuit, a delay tracking circuit containing a digital discriminator connected to the mixer output of the PLL circuit, which is designed to simplify and speed up the search and capture of a pseudo-random signal while ensuring separate pseudo-random sequence frequency search and simplifying tracking filter the delay consists of an incoherent discriminator connected to the shift register of the delay tracking circuit, the output of the nth trigger of which 5 is connected to the phase demodulator of the PLL circuit. BUT  /,