SU705901A1

SU705901A1 - Storing device

Info

Publication number: SU705901A1
Application number: SU762337573A
Authority: SU
Inventors: Г.Д. Софийский; Р.В. Смирнов
Original assignee: Предприятие П/Я М-5769
Priority date: 1976-03-23
Filing date: 1976-03-23
Publication date: 1982-01-07

Description

(54) ЗАПОМИНАЮЩЕЕ УСТРОЙСТВО(54) STORAGE DEVICE

Изобретение относитс к области вычислительной техники.This invention relates to the field of computing.

Известно запоминающее устройство (ЗУ) на динамических элементах IJ, недостатками которого вл ютс наличие запретов по обращени м во врем регенерации информации в элементах Пам ти, низка производительность работь и невысокое быстродействие.A memory device (IU) on dynamic IJ elements is known, the disadvantages of which are the presence of inhibitions during the regeneration of information in the memory elements, poor performance and low speed performance.

Наиболее близким к предлагаемому устройству техническим решением вл етс ЗУ, содержащее элементы пам ти на динамических триггерах, первый счетчик, адресные шины, первые и вторые числовые шины 2.Closest to the proposed device, the technical solution is a memory device containing memory elements on dynamic triggers, the first counter, the address buses, the first and second numerical tires 2.

Недостатками ЗУ вл ютс наличие прерываний по обращени м дл регенерации информации в элементах пам ти, низка производительность работы и невысокое быстродействие. Необходимость проведени циклов регенерации, во врем которых запрещено обращение к элементам пам ти, сильно сужает область применени устройства. В частности, затруднено использование устройства в вычислительных системах, работающих в реальном м.асштабе времени, хот применение его в этих системах дало бы существенный выигрыш по р ду параметров, таких как быстродействие , мощность, надежность и габариты .The disadvantages of memory are the presence of interruptions in requests for the regeneration of information in the memory elements, low performance and low speed. The need for regeneration cycles, during which the access to the memory elements is forbidden, greatly narrows the field of application of the device. In particular, it is difficult to use the device in real-time computing systems, although its use in these systems would give a significant gain in a number of parameters, such as speed, power, reliability, and size.

Цель изобретени - повысить быстродействие устройства.The purpose of the invention is to increase the speed of the device.

Это достигаетс тем, что устройство содержит второй счетчик, дешифраторы, шифратор и двухканальные переключатели , первые входы которых соединены с адресными шинами, вторые входы - с выходами первого счетчика, третьи входы - через один дешифратор с выходами второго счетчика, выходы двухканальных переключателей соединены с первыми входами соответствующих элементов пам ти, вторые входы которых через шифратор, а выходы через другой дешифратор подключены соответственно к первым и вторым числовым шинам. .This is achieved in that the device contains a second counter, decoders, an encoder and two-channel switches, the first inputs of which are connected to the address buses, the second inputs - to the outputs of the first counter, the third inputs - through one decoder with the outputs of the second counter, the outputs of two-channel switches are connected to the first the inputs of the corresponding memory elements, the second inputs of which are through the encoder, and the outputs through another decoder are connected to the first and second numeric buses, respectively. .

На чертеже приведена стрз ктурна схема устройства.The drawing shows the page of the device circuit.

Устройство содержит элементы 1 пам ти , первый счетчик 2, адресные шины 3, первые числовые шины 4, вторые числовые шины 5, второй счетчик 6, дешифраторы 7 и 8, шифратор 9 и двухканальные переключатели 10.The device contains memory elements 1, first counter 2, address buses 3, first numeric tires 4, second numeric buses 5, second counter 6, decoders 7 and 8, encoder 9 and two-channel switches 10.

Устройство работает следующим образом .The device works as follows.

Claims

The address (read or write) address code is fed through address buses 3 to the first c) soda switches W, to the second inputs of which from the outputs of counter 2 the regeneration address code is applied. The decoder 7, in accordance with the code arriving at its inputs from the outputs of counter 6, excites the third switch inputs of the switches 10. Reset: at and the first inputs of the corresponding memory elements I, forming one of the bits of the charger, pass the code of the regeneration address, and on the first inputs of the remaining memory elements 1, the address address code passes. At the same time, in the recording mode, the code of a number received by the first 4-digit keys 4 of the inputs of the encoder 9 is converted by it into a redundant number code, allowing correction of multiple errors. Since during the regeneration cycle into the memory elements 1, in which information is regenerated, the code cannot be recorded, the redundant number code coming from the output of the encoder 9 is recorded only in those memory elements 1, the first address of which receives the address address code . As a result, the redundant code of the number in which there can be one erroneous bit (a one-time error) is written to the memory elements at the address of the address. In the read mode, the memory elements 1, forming one of the bits of the memory in which the information is regenerated, can either coincide or not coincide with the elements of the memory I, in which the information was regenerated when writing the number code. In the first case, the read redundant code of a number may contain one erroneous bit (one time error), and the BQ in the second case two erroneous bits (two time error). The readable redundant code of the number is output from the outputs of the memory elements 1 to the inputs of the decoder 8, which corrects it, which is possible due to the correcting ability of the redundant code. The corrected numberless code of the number then enters from the outputs of the decoder 8 to the second numeric tires 5, i.e., to the output of the memory. Thus, in the proposed memory, information regeneration cycles and circulation cycles are combined in time, i.e., during the regeneration cycles, there are no interruptions in accessing the memory. This makes it possible to significantly increase the performance of pa6oTbii memory and its speed. In addition, the elimination of interruptions for the regeneration of information greatly expands the area of application of memory, which allows it to be used in real-time computing systems. As a result, the performance, power, reliability, and dimensions of the computing system are significantly improved. The invention includes a memory device containing memory elements on dynamic triggers, the first counter, the address lengths, the first and second numeric plugs, characterized in that, in order to improve the speed of the device, it contains the second counter, decoders, encoder and two-channel switches, the first inputs which are connected to address buses, the second inputs are connected to the outputs of the first counter, the third inputs are connected via one interface to the outputs of the second counter, the outputs of two-channel switches are connected to the first inputs the corresponding memory elements, the second inputs of which are through the encoder, and the outputs through another decoder are connected respectively to the first and second numeric buses ...-..., v: ----:; ... v, -.:,. : -;.-.- Sources of information taken into account for our examination: 1. US patent no. 3,760,379, cl. 340173 R 117/00, 1972.

2. Computer Design, July 1975, p. 63, fig. 1, s. 67, fig. 7 (prototype).