SU705692A1 - Error detector - Google Patents

Description

one

The invention relates to electrical communication and can be used in instruments for determining the error rate in linear paths of digital transmission systems.

The known detector contains serially connected switch, shift register and the first half-adder, the output of which is connected to the second input of the switch, as well as the second half-accumulator and error integrator connected in series, the output of which is connected to the control input of the switch 1.

However, this detector has insufficient error detection accuracy.

The purpose of the invention is to improve the accuracy of error detection. To do this, a delay element and Transmitter code converter, the input of which is connected to the output of the first half-adder which is connected to the output of the delay element, the input of which is connected to the input of the error detector.

The drawing shows the structural scheme of the proposed device.

Error Detector contains

5 switch 1, shift register 2, two half-adders 3 and 4, transfer code converter 5, delay element 6, integrator 7 errors. The device works as follows.

0 way.

The error detector, depending on the state of the switch 1, can be in one of two modes — a phasing mode or a measurement mode. In the phasing mode, the input signal is fed to the input of the shift register 2, and the feedback circuit between the output of the first half-adder 3 and the input of the register 2

pa 3 OMK Well, that, and for all; and 6; in one odd signal; a long length of time interval from errors and not containing code inserts (i.e., a segment of a pseudo-random sequence (PSI), in which there are no combinations from p + 1 and more consecutive zeros), at the output of the first A PEETummator 3 is formed the same, free from code inserts, dtpesbk riCri. Converter 5 code. transmissions over this:

J3Tpe3Ka does not enter into the PSP Vega11Sh to; 6 JEfa il ya eODy v6yrogo half-shuimato-. Equal and common-mode memory bandwidth arrives at stage 4 (the delay introduced by the transducer 5 of the transmission code is compensated by delay element b). At the same time, at the output of the second half-adder 4, there are no error pulses and after a time determined by a constant 7 errors in the integrator's belt, the switch 1 will close;

 connection between the half-adder 3 and the register 2 and disconnects the input of the register 2 from the input of the error detector. In the formation of the generator, the PSP will continue to form it: PSP, s and nfa 3 ya and with him. PS P P, but not containing code inserts. When prVLenin at the output of the first half adder 3 segments of the SRP containing n + 1 or more consecutive

zeros, the transmitter 5 of the transmission code enters into these segments the code BeFgyK and, kS Fychyyo in with t (t:: at the same time points

its input signal. In the same way, in the absence of errors in the input signal, the second half-adder 4 receives identical PSS with identical red inserts and, therefore, the output of the half-adder 4

no / - - - - T - --- The occurrence of each error in the input signal causes the appearance of SN

705 (592

on the halfway out side 7 / 1mator 4, which is the output Error Detectors.

During normal operation (interruption of communication, failure of the SUNHE) of identification, etc., an error burst appears at the output of the error detector, switch 1, controlled by integrator 7, switches the error detector to the phasing mode until an error occurs at the input Undistorted signal, after which the revised process is repeated.

Claims (1)

1. Gordon F.G-, Nurmukhamedov L.Kh. On phased sensors test testers. Wired radioelectronic technology, vol. ki 6, 1965 (prototype). esrjir BH -jL-tti - “fri:. isfeiiii -.iiiiiii; - - - ™ - -.