SU1300650A1 - Device for checking regenerator of digital communication system - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to reduce the detection time of a faulty generator. The device contains a receiver I, a regenerator 2, a clock frequency selector 3, two ELTs 4 and 12, (two transducers 5 and 10 codes, counter 6, El I 7, shift register B, decoder 9, trigger 11 and transmitter 13. The goal is achieved by implementing the synchronization pattern present in the linear signal structure of the pulse code modulation, and the frequency of occurrence of this sync pattern. For this, the devices OR 4 and 12, the converters 5 and , 10, counter 6, register 8, decoder 9 and trigger II, which are used to read and vivo Recording control information without affecting the communications yl 1 i (L a:.. from O5 Sta

Description

1I

The invention relates to telecommunications and can be used in communication systems with pulse code modulation (PCM) in the transmission of signals via both wired and fiber-optic communication lines.

The purpose of the invention is to reduce the detection time of a faulty regenerator.

The drawing shows the structure of the electrical circuit of the device for controlling - the regenerator of the digital communication system.

The device contains a receiver 1, a regenerator 2, a clock frequency selector 3, the first element OR 4, the first transducer 5 of the code, counter 6, the And 7 element, the shift register 8, the decoder 9, the second transducer of the 10 code, trigger 11, the second element OR 12, the transmitter 13.

The device works as follows

In the structure of a linear PCM signal, there is always a synchronization group intended for synchronization of channel allocation equipment. The location and code of this sync group is known in advance. To separate this sync group, the first code converter 5 is used, the shift register 8 and the decoder 9. The first code converter 5 is designed to convert a linear signal into a digital signal known as NRZ. The NRZ signal passes through the shift register 8, and at the outputs of the decoder 9 signals are obtained indicating sync groups are present, and at the first output of the decoder 9 the signal appears when there is a sync group in the forward NRZ code, and at the second output when the synchro groups in inverse code. The moment of occurrence of the synchro-group using the second and first elements OR 12 and 4 is fixed by the counter 6, in particular, the counter 6 is set to zero and then the clock pulses are counted. The number of pulses that must be detected by the counter 6 is determined by the location of the synchro-group and, as indicated, is known. In this connection, a chain consisting of two elements, OR 4.12 and counter 6, binds to the frequency of occurrence of this sync group. By the time of 50 /

Picture 1 of the next sync group, counter 6, gives permission to the decoder 9 for operation, and thus excludes the probability of a random response from the sync pattern-like code pattern. The synchro groups allocated by the decoder 9 can be in both the forward and inverse codes. Accordingly, the first and second outputs of the decoder 9 receive pulses arriving at the trigger inputs, the output of which eventually results in a digital signal varying with the frequency of the sync group. With the help of element AND 7, if there is a resolution from the output of the second element OR 12, it is possible to perform the inversion of the synchrogroup located in the shift register 8. To do this, a binary signal is supplied to the first input of the device (the address of the regenerator, information about its state coming from the sensors) and to the second input of the device, a signal is enabled to write the characters of the control information to a linear signal at the positions of the sync groups. Each of the sensors (not shown) provides binary information: O is the norm, 1 is an accident (pre-warning). At the time of the occurrence of the synchro group in the shift register 8, the second element OR 12 imposes an enable signal on the element AND 7 and, depending on the character of the control information that needs to be transmitted, the synchro group transforms into a direct or inverse one.

The converted sync group is fed to the input of the second converter 10 of the code, where the digital line signal is converted from the NRZ code to a linear code, the same as the input of the first converter of the 5 code. The obtained linear signal from the output of the second converter 10 of the code is fed to the input of the transmitter 13 and further to the communication line. Thus, the reading and writing of control information is carried out without disturbing the communication.

Claims (1)

Invention Formula A device for controlling a regenerator of a digital communication system, containing a series-connected receiver and a regenerator, the first input of which is connected to the input of the clock frequency selector, the output of which is connected to the second input of the regenerator, the element And the transmitter, which is In order to shorten the detection time of a faulty regenerator, the first code converter is connected in series, the shift register and the second code converter, the output of which is connected to the transmitter input, a trigger and connected in series the first element SH, counter, decoder and the second element OR, with the regenerator output connected to the input of the first code converter, the output of the AND element connected to the second input of the shift register, output Editor E. Sligan Compiled by A. Seselkin Tehred I.Popovich Proofreader A, Tsk Order 1161/57 Edition 639Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 the second element OR is connected to the first inputs of the element AND and the first element OR, the output of the counter is connected to the second input of the first element OR, the bit outputs of the shift register are connected to the corresponding information inputs of the descrambler, the second output of which is connected to the second input of the second element OR and to the first input trigger, the second input of which is connected to the first output of the decoder, and the other code of the clock divider is connected to the second inputs of the counter, the first and second code converters and to the third input ode shift register.