SU552704A1 - Frequency divider with automatically variable division factor - Google Patents

Description

The invention relates to pulse radio engineering and automation and can be used in control devices of drawing machines, in particular, for acceleration and deceleration of stepper motors.

Controlled frequency dividers are known in which the change in the division factor is specified externally, either by a predetermined program or by special blocks.

One of the known devices contains counters, devices for lowering the reverse code and logic elements.

However, in such a device, the change in the division ratio is set externally according to a given program, which requires the additional development of special devices for setting programs to change the division ratio.

Another known device is more perfect and contains a decoder, a binary frequency divider, the first input of which is connected to the input bus, the second input through the parallel code block to the first output of the reversible counter, and the output to the input of the parallel code recording unit and to the first inputs of the elements And, the outputs of which are connected to the inputs of the reversible counter.

However, such a device is unsuitable for stepper motor control circuits when the latter have worked out the number of steps that are not a multiple of twice the maximum value.

numbers in a reversible counter, for example, in automatic graphic machines.

The purpose of the invention is to expand the functional capabilities of the frequency divider. This is achieved by introducing a comparison unit, a subtracting counter and a switch into the proposed frequency divider with automatically changing division ratio, the first input of the counter reading counter is connected to the output of the binary frequency divider, the second input is connected to the code bus, and the output is to the decoder input and the first input of the comparison unit, the second input of which is connected to the first output of the reversible counter,

and the output — with the first input of the switch, the second input of which is connected to the output of the decoder, the third input — to the input bus, and the outputs — to the second inputs of elements I. The drawing shows a structural electrical circuit of the proposed frequency divider with an automatically changing division factor.

The proposed device contains a binary frequency divider 1, a parallel code recording unit 2, a reversing sensor 3, a subtracting counter 4, elements 5 and 6, a comparison block 7, a decoder 8 and a switch 9 which contains triggers 10 and 11 and elements 12 and 13 (14-code bus).

The frequency divider works as follows.

The pulses of the external oscillator with frequency FB are fed to the input of the double frequency splitter 1. The overflow pulse from the output of binary frequency splitter 1 through block 2 rewrites the direct code from reversing counter 3 to binary frequency divider 1, enters the input of detracting counter 4 and through element 5 arrives at the summing input of the reversible counter 3. The frequency / output at the output of the binary frequency divider 1 increases monotonously as the code in the reversing counter 3 increases and is set to the maximum at the maximum value of and a down counter 3.

If the value of the code in subtractive counter 4 is greater than twice the maximum code of the reversible counter 3, then the overflow pulse from the output of the reversible counter

3 after setting the maximum code in it sets the trigger 11 to one state and thereby removes the resolving potential from the zero output of the trigger 11 to the input element I 5, prohibiting the passage of pulses to the summing input of the reversing counter 3. From this moment the maximum frequency of the pulses from the output the binary frequency divider I is maintained until the code in subtractive counter 4 is equal to the maximum code of the reversible counter 3. After comparing the codes, block 7 provides the resolving potential at elec Ment 12, the pulse from the output of which sets the triggers 10 and 11 into a single state, as a result of which a single potential output of trigger 10 enters the resolving potential per element AND 6. The pulses from the output of binary frequency divider 1 through element 6 begin to flow to the subtracting input reversible counter 3 and reduce the code value in it, which leads respectively to a monotonous decrease in the output frequency / output divider.

When the code in subtractive counter 4 becomes zero, the decoder 8 will apply the enable potential to element 13 for passing the FBK pulses to reset the triggers 10 and 11 to the zero state and returning the frequency divider to its original state. To perform the next cycle of operation, the frequency divider feeds the new code on code bus 14 into subtractive counter 4.

If the code value in the subtractive counter

4min double the maximum value

reversible counter code 3, the frequency of the pulses / outputs from the output of binary frequency divider 1 increases to such a value until the increasing code value of reversing counter 3 becomes equal to the decreasing code value of the subtractive counter 4. After comparing the codes, block 7 issues a resolution note on the And 12 element to pass the input frequency pulse FB-S.

on the installation of the triggers 10 and And in one state. The resolving potential from the zero output of the trigger 11 is removed from the And 5 element, and the resolving potential from the single output of the trigger 10 is fed to the And 6 element.

From this point on, reversible counter 3 starts working to reduce the code in it, thereby monotonously reducing the frequency of the pulses. RBY from the output of the binary frequency divider 1. The work cycle of the frequency divider ends similarly as described above when the bullet code appears in the subtracting counter four.

The frequency at the output of the binary frequency divider 1 is equal in all cases

R

77 „BX

out

where n is the number of bits of the binary divider

frequency 1; L - the number in the reverse counter 3.

Claims (1)

Invention Formula A frequency divider with an automatically variable division factor, containing the decoder, the binary frequency divider, the first input of which is connected to the input bus, the second input through the parallel code recording unit to the first output of the reversible counter, and the output to the input of the parallel code recording unit and to the first inputs of the And elements whose outputs are connected to the reverse inputs a counter, characterized in that, in order to extend the functionality, a comparison unit is introduced into it, subtractive counter and switch, the first input of the subtractive counter is connected to the output of the binary frequency divider, the second input is connected to the code bus, and the output is connected to the input of the decoder and the first input of the comparator unit, the second input of which is connected to the first output of the reversible counter, and the output is with the first input of the switch, the second input of which is connected to the output of the decoder, the third input to the input bus, and the outputs to the second inputs of the elements I.