SU516021A1 - Device for compensating mechanical oscillations during optical-mechanical image scanning - Google Patents

Description

comic element “OR 22, trigger 23, delay element 24 and prohibition logic element 25.

The device works as follows.

When a video signal containing a cross-linking impulses (line phasing pulses that have any distinctive sign from the informational ones: a large amplitude, a different frequency, etc.) arrives at the device input, it converts in the imaging unit 1 into a two-level signal, while using a selector 3 pulses of "stitching" are selected as the starting pulses of the device, the rising edges of the pulses of "stitching", and as dining rooms - their leading edges. The amplitude-formed video signal is fed to the sampler 2, where simultaneously the strobe pulses from the coordinate optical sensor 4 are fed.

Using sensor 4, the line of the analyzed image is conventionally divided along the length into identical elementary areas — raster elements, the length of which does not exceed the width of the scanning element.

The discretized video signal is fed to the electronic key 6 of the switching unit 5, which simultaneously with the key 7 is opened by the starting pulse from the selector 3. The discretized video signal passes to the inputs of the logical elements 11 and 10 of the reversing counter 8.

The part of the pulse sequence of the video signal corresponding to the number of raster elements located in the swing zone is memorized by the memory cells 17.

At the same time, the number of memory cells is equal to the number of raster elements located in the swings area. From a certain point in time, the completed information begins to be read from memory cells 17 while simultaneously recording the video signal into the empty cells, taking into account the read priority with respect to the recording. Such a memory cell operation allows the creation of a time buffer in which the temporal irregularities in the video signal pulse sequence caused by mechanical oscillations are quenched.

On the first strobe pulse, the first information pulse of the Video signal through the rightmost logical element “And 11 passes a priority block 12, arrives at the logical element“ OR 15 and prohibits the input of the inhibit logic element 14. This causes the memory cell 17 to be turned off for the duration of the recording the first information pulse (through the element “OR 15). After the information has been recorded in memory cell 17, its communication with the neighboring memory cell is restored. The same process occurs when information is written to all subsequent memory cells until the information is written to the last memory cell.

At this time, the pulse from the decoder 9 through the prohibition logic element 25 and the logic element OR 22 turns on the electronic key 19. The reading of the information from the memory cells begins, as with a shift register. At the same time, a trigger is triggered with separate inputs 23, including an AND 20 logic element with its output pulse and a prohibition 25 logic element through delay element 24.

The start of the reading is controlled by the phasing counter 21. For this purpose, through the key 19 and the logical element 20 the pulse generator 18 outputs a sequence of pulses.

Through the key 19, clock pulses are fed to the inputs of priority blocks 12, to the read inputs of memory cells 17 and to the reversible counter 8. Each priority block

built in such a way that at the moments of the clock pulses, the passage of information pulses into the memory cells is forbidden through them.

On the first clock pulse, the information is shifted, filling the memory cell one space to the right. In this case, the first information pulse appears at the output of the device, and one memory cell is released. Simultaneously in reverse

the counter 8 subtracts one pulse, and the decoupled switch of the descrambler shifts by one to the right. With the arrival of the next Fia pulse, the addition bus performs the reverse re-switching of the dshifferator buses, i.e., it becomes possible to record an information pulse in the memory after the shift of the memory cell 17. Thus, the reversible counter 8 always monitors the input of each release 1, it

memory cells 17, making it possible to write an information pulse corresponding to a given moment of scanning into it.

Writing information with its simultaneous reading is done before arriving with

pulse selector 3, corresponding to the end of the analyzed line of the image on keys 6 and 7, which are opened. The up / down counter is clocked in 8 clock pulses from generator 18 into

initial position.

Upon completion of reading the line by the signal of the decoder 9, the key 19 is opened, and the pulse generator 18 is turned off. The remaining lines are read and written in the same way.

Claims (1)

Invention Formula Device for compensating mechanical oscillations during optical-mechanical scanning image containing a sampler connected to an optical coordinate sensor, a switching unit and through a driver with a phase selector switch connected to a switching unit, a reversible counter connected to the unit switch and with the decoder connected to the block of logic elements "And, and with the switch block, a pulse generator connected through the logical element" And, the other input of which is connected to the trigger and to the delay element, the phasing counter connected to one of the inputs of the logic element " OR, the other input of which is connected to a trigger and a delay element through a prohibition logic element, and characterized in that, in order to increase the reliability of the device, it contains priority blocks, the inputs of each which are connected to the block of logic elements "And, connected to the switching unit, with a decoder, with a reversible counter and through a key, the other inputs of which connected to the decoder and the logical element "OR, with a pulse generator, information recording control unit connected to priority blocks, n memory block, and connected to the recording control block information and to the priority blocks, the trigger input is connected to the decoder, and the output of one of the priority blocks is connected to the memory block. d, di I p