SU489154A1 - Memory device - Google Patents

Description

(54) STORAGE DEVICE

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The invention relates to computing and can be used in digital computers.

A memory device is known that contains the address register of the page, the output of which is connected to the input of the page decoder, the register of the address of the word, the output of which is connected to the input of the word decoder. The output of the word decoder is connected to one of the inputs of the address decoder, the other input of which is connected to the output of the page decoder. The outputs of the address decoder are connected to the inputs of the first recording elements, the outputs of which are connected to the error inputs of the storage device.

In a known memory, codewords are written into numerical cells without taking into account the statistics of the distribution of codewords in the array.

The purpose of the invention is to increase the speed and density of recording information in the device.

This is achieved by the fact that the memory device contains an additional descrambler, the elements of the prohibition of recording. Outputs

the second recording elements are connected with one of the inputs of the recording prohibition elements, the other inputs of which are connected to the outputs of the first recording elements, and the outputs of the recording prohibition elements are connected to other inputs of the accumulator, the output of the page address register is connected to the input of an additional 1-decoder, the outputs of which are connected to inputs of the second entry elements.

The drawing shows a block diagram of a memory device in which information is recorded that contains two pages but four three words in each.

The storage device contains the register of the address of page 1, the output of KOTopoi o is connected to the input of the decoder of page 2, the register of the address of the word 3, the output of which is connected to the input of the decoder of the word 4.

The output of the decoder of word 4 is connected to one of the inputs of the decoder of apache 5, the other input of which is connected to the output of the decoder of page 2. The outputs 6-13 of the decoder 5 are connected to the inputs of the first recording elements 14 and 15, 1 designated respectively for recording the least likely and O. Outputs the first elements of the record 14 and 15 are connected to one input of the accumulator 16. The outputs 17 and 18 of the additional decoder 19 are connected to the inputs of the second elements of the record 20 and 21, intended: for recording the most vertex and O, respectively. The distributor 19 is connected to the perHC pa output of the page 1 address. The outputs of the second elements of the registry keys 20 and 21 are connected to one of the inputs of the recording inhibit elements 22 and 23, whose other inputs are connected to the OUTPUTS of the first recording elements 14 and 15 The outputs of the recording inhibit elements 22 and 23 are connected with other inputs of the drive 16,

The presence or absence of the connection of the first elements of the record 14 and 15 with the outputs

6-13 of the address decoder 5, as well as the second elements of the record 2O and 21, with outputs 17 and 18 of the additional decoder 19, are determined by the recorded: information.

The words of the first page are written using the outputs 6-9 of the address decoder 5 and the output 17 of the additional decoder 19, and the words of the second page are recorded using the outputs 10-13 of the address decoder 5 and the output 18 of the additional decoder 19. 2O and 21 output 17 of the additional decoder 19 recorded the word BUT, and the output in the first elements of the record 14 and 15 outputs 6-9 decoder address 5 recorded respectively Words: 110, SO, 11 and 010, and outputs 10-13 - words respectively: 000, 100, 101 and BUT.

The storage device operates as follows.

The code combination of the page address comes from the address register of page 1 I to the decoder of page 2 and the additional decoder 19, the code combination of the address of the word goes from the address register of word 3 to the decoder of the word 4. The decoder of page 2 and the decoder of the word 4 excite one, from inputs 6-13 address 5 decoder, for example, output 12. According to the code combination of the page address, one of outputs 17 or 18 is selected, for example, 18, additional decoder 19, exciting the second recording elements 20 and 21. In accordance with the connection of output 12 The address decoder 5 initiates the first elements I of entries 14 and 15, which control the current control and prohibition circuits 22 and 23.

The signals from the outputs of the first recording elements 14 and 15, respectively, prohibit the passage of signals from the outputs of the second recording elements 20 and 21 through the write inhibit circuits 22 and 23. Signals from the outputs of the excited first recording elements 14 and 15 are recorded in drive 16 through one of its inputs. In that case, if the control signals from the outputs of the first recording elements 14 and 15 to the same inputs of the write inhibit circuits 22 and the write inhibit circuits 22 and 23 are recorded in the drive 16.

When, for example, selecting the output 12 of the address decoder 5 and the output 18 of the additional decoder 19, the SO code code is found from the second elements of the record 2O and 21, the first two characters of which are written to the drive 16, and the last character does not pass through the write inhibit circuit 22, so As from the first element of the record 14, the prohibiting signal arrives at the recording prohibition scheme 23 of this bit. The signal from the output of the first element of record 14 is fed to the input of this bit of drive 16.

Drive 16 is written by code combo 101.

Similarly, it works remember the device when you select any other word on a page.

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Forla of invention

A storage device containing the register of the page address, the output of which is connected to the input of the page decoder, the register of the address of the word, the output of which is connected to the input of the word decoder, and its output is connected to one of the inputs of the address decoder, the other input of which is connected to the output of the page decoder, the outputs of the decoder addresses are allocated to the inputs of the first recording elements, the outputs of which are connected to one input, accumulate; 7I, characterized in that, in order to increase speed and increase the information recording density in device, it contains an additional decoder, recording prohibition elements and second recording elements, the outputs of which are connected to one of the inputs of 3d elements - Preta recording, their other inputs are connected to the outputs of the first recording elements, and the outputs of recording prohibition elements are connected to other inputs of the accumulator . The address of the page address is connected to the input of an additional decoder, the outputs of which are connected to the inputs of the second elements (records.