SU450368A1 - - trigger - Google Patents

Description

one

This invention relates to computing devices and. digital automation.

There is a known 5-trigger containing a bistable cell made on AND-NOT gates, to each arm of which a coincidence circuit is connected. Some of the inputs of the coincidence circuits are combined and connected to the clock pulse bus, the other inputs are connected to the information buses. In such a trigger, b) the effect is limited by the total switching time of the logic elements of both arms of the bistable cell.

In order to improve the speed in the proposed trigger, an additional logical element "AND-NOT, the direct output of which is connected to the additional inputs of the logical elements" AND-NOT a bistable cell, and the inverse output is connected to a clock pulse bus, is installed.

The drawing shows the functional diagram of the proposed / 5-trigger.

The trigger contains a bistable cell made on the AND-1 and 2 logic elements with coincidence circuits 3 and 4 connected to the inputs of each arm, one inputs of which are combined and connected to the clock 5, and others are connected to the information bus 6. Pr My output 7 of the logical element “IS – NE 8 is connected to the auxiliary input of each zero of a bistable cell, and the inverse output is connected to the bus 5 of the clocking pulse.

If, in the absence of a clocking pulse (information recording pulse), the input logic level 8 has a logic level "O, then the output level of the bistable cell will be logic level" 1.

Due to the presence of a logical "1" at the clocked input of the matching circuits, the signals arriving at the information buses in the form of a logical "O and logical" 1 are inverted and output to the inputs of the bistable cell.

At the time of arrival at the additional inputs of logic elements 1 and 2, the clocking pulse in the form of a logical "1 occurs

the coincidence of the logical "1 on three inputs of one of the logical elements 1 and 2, which leads to a change in the level of its output, appears logical" O. In this case, a bistable cell is turned on, as a result of which the incoming information is recorded at the outputs. Simultaneously with the operation of the bistable cell, the coincidence circuits of the clocked input are switched off, thus eliminating the influence of information signals on the state of the big cell.

Subject invention

An S-flip-flop that contains a bistable cell on "AND-NAND" logic gates, to each arm of which coincidence circuits are connected, one inputs of which are combined and connected to the clock bus, and the other inputs are connected to information buses, characterized by increase the speed, it has an additional logical element "AND-NOT, the direct output of which is connected to the additional inputs of the logical elements" AND-NOT a bistable cell, and the inverse output - to the clock pulse bus.