SU439812A1 - Device for interrupting programs - Google Patents

Description

(54) DEVICE FOR INTERRUPTION OF PROGRAMS

The invention relates to computing and, in particular, to devices for interrupting programs.

A device for interrupting programs is known comprising an interrupt register, a circuit for collecting interrupt signals connected to the interrupt output of the device, an encoder, a register of sandwiches whose inputs are connected to the first ground inputs of the device, and exits to the first group of inputs of the enabled interrupt detection circuit.

The known device for interrupting programs has a drawback: when signals are received with a long duration and with front chatter, special drivers must be incorporated into the device, which increases equipment costs and reduces device reliability.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that the device contains control triggers, the first, second, third and fourth groups of circuits "And, the first, second and third groups of inverters, the control inverter, the first and second delay elements, and the second group of inputs of the device is connected to the inputs of the corresponding first groups of inverters, the third group of inputs of the device is connected to the first inputs of the corresponding second group

inverters, the second inputs of which are connected to the output of the first delay element; the outputs of the first and second groups of inverters are connected to the single inputs of the corresponding control triggers, the second and third groups of device inputs are connected to the first inputs of the corresponding first AND circuit, the second inputs of which are connected via a control inverter to the interrogative input of the device , the output of which is connected to the response output of the device, to the input of the second delay element and to the first inputs of the second group of circuits "And, the second inputs of which are connected to the yen with the corresponding they encoder inputs; the outputs of the second group of "AND" circuits are connected to the bullet inputs of the corresponding control triggers and interrupt register triggers, the single inputs of the control triggers

0 is connected to the third inputs of the corresponding first group of AND circuits, the outputs of which are connected to the single inputs of the corresponding triggers of the interrupt register, the single outputs of which are connected to the inputs of the interrupt signal acquisition circuit n from the second

5 ground inputs of the circuit for detecting allowed interruptions, the outputs of which, except the first and last, are connected to the first inputs of the corresponding third group of schemes “AND

0 p through the corresponding third group of inverters — with the first inputs of the corresponding fourth group of circuits — the outputs of each of the fourth group of circuits “And” are connected to the second inputs of one of the third and one of the fourth groups of “And circuits connected with the subsequent output of the detection circuit for allowed interrupts, the first output of which is connected to the corresponding input of the encoder and through the corresponding inverter of the third group of inverters to the second inputs of one of the third and one of the fourth groups of AND circuits connected with the subsequent output of c We allowed the detection of interrupts, the latter output is connected to a first input circuit corresponding "And from the third group schemes" And, the second input coupled to an output of one of the fourth group of circuits "and associated with the previous output of the circuit for detecting interrupt resolutions Display resolution; the outputs of the third group of circuits "And connected to the inputs of the encoder, the outputs of which are connected to the outputs of the device.

The block diagram of the proposed device for interrupting programs is shown in the drawing.

The device contains the interrupt register /, triggers interrupt 2i-3p, the first group of circuits "And 3i - t3, i, circuit 4 for detecting allowed interrupts, the second group of circuits" And, the third group of circuits "And, the fourth group of circuits" And 7j - 7i, first, second 1-Sj and third group of inverters 9j-9 ', encoder 10, circuit /./ collection of interrupt signals, protection register 12, polling inverter 75, first delay element 14, second delay element: 75, control triggers

The drawing shows the following tires: the first group of input buses ./7, the second group of input tires, / 5g -18 n, the third group of input bushes, the output interrupt bus., The answer bus 20, the polling bus 2 /, the device output tires 22, the output tires, 25) -23p patterns for detecting allowed interrupts.

The device works as follows.

In the absence of interrupt signals, the device is in the initial state.

When a higher priority interrupt signal is received, for example, on input 5g, trigger 5, the interrupt register /, through the circuit, is set to state "1. The signal from trigger 2 goes to circuit 4 for detecting allowed interrupts. From the output 23i of this circuit, the signal goes through the di inverter to the circuit, as well as to the circuit. The signal taken from the circuit output through the circuits -t-f- «H 7j ,, blocks all 6t-i-61 circuits. Since the signal taken from output 231 is the highest priority, a single signal is output only at the output of circuit 61. This signal is fed to the input of the encoder 10, the outputs of which 22 are formed

higher priority interrupt code.

The signal from the single output of the trigger 2 enters the circuit // of the collection of interrupt signals, from the output of which .7: 9 enters the computer. By this signal, the computer generates a polling signal, which is used to read the number of the highest priority interrupt number to the computer. In addition, the interrogation signal is fed to the interrogator input 21 of the interrupt device and through the interrogation inverter ./i5 to the circuit input, as well as through the second delay element 75 to the response bus 20 and to the circuit input. The magnitude of the delay of the J6 element is equal to the total delay of the signal passing through the scheme 4 identifying the allowed interrupts, the scheme, and the JO encoder. In this case, a signal is removed from the output of the circuit, which resets the trigger 2i and sets the state to the control trigger. The signal taken from the single output of the rs-igger control 16i blocks further receipt of the interrupt signal at the input of the trigger 2 through circuit 3. until the signal on the bus M B 1 terminates at the moment when the interrupt signal on the bus / 5; stop, the trigger 7 i through the inverter .8i is set to the state "1.

Thus, the proposed device, upon receipt of the interrupt signal, immediately forms the code of the number of the higher priority interrupt. The formation of this code is performed on a combinational circuit, which allows, on the one hand, to reduce the time required to receive it, and on the other hand, to unload the computer. As is clear from the description of the operation of the device, the duration of interrupt signals without chatter of fronts can be arbitrarily long. This circumstance makes it possible to refuse additional formers commonly used in known devices.

When a higher-priority interrupt signal arrives with edge bouncing, for example, via the i5j bus, the device operates as follows.

The control trigger 16j is in a single state, and from the polling inverter 13 a single signal arrives at the circuit. The circuit is triggered, and the trigger 2j of the interrupt register 7 goes to the state "1.

After this interruption is serviced, a single signal from the output of the circuit 6j is fed to the circuit, to the second input of which the interrogation signal arrives through the second delay element 15 from the 2: 1 bus. The output of the circuit resets the control trigger 16j and the trigger 2j to the zero state. The zero signal from the output of control trigger 16j is fed to the input of the circuit, thereby blocking the input signal, if it has not yet ended. The polling signal through the first delay element iM (the delay of which is obviously greater than the duration of the input signal, including the fronts duration) and the inverter 8j enters the single control trigger input 16 / and sets it to the unit state, thereby preparing the device for further work.

Subject invention

A device for interrupting programs containing its interrupt register, an interrupt signal collection circuit connected to the device interrupt output, an encoder, a lock register, and inputs whose inputs are connected to the first group of device inputs and outputs to the first group of inputs of an enabled interrupt detection circuit. , in order to increase reliability, the device contains control triggers, AND circuits, inverters, control inverter, delay elements, the second group of device inputs connected to the corresponding inputs, the first group of inverters to it, the third group of inputs of the device is connected to the first inputs of the corresponding second group of inverters, the second inputs of which are connected to the output of the first delay element; the outputs of the first and second groups of inverters are connected to the single inputs of the corresponding control flip-flops, the second and third groups of device inputs are connected to the first inputs of the corresponding first AND circuit, the second inputs of which are connected via a control inverter to a polling input of the device, connected to the input of the second delay element, the output of which is connected to the response output of the device, to the input of the second delay element and to the first inputs of the second; groups of circuits "And, the second inputs of which are connected to the corresponding the inputs of the encoder; the outputs of the second group of circuits "AND" are connected to the zero inputs of the corresponding control triggers and triggers of the interrupt register; the unit outputs of the control triggers are connected to the third inputs of the corresponding first group of circuits "AND, whose outputs are connected to the single inputs of the corresponding triggers of the interrupt register, whose single outputs are connected to the inputs interrupt signal acquisition circuitry and with the second group of inputs of the detected interrupt detection circuit, the outputs of which, except the first and last, are connected to the first the inputs of the corresponding third group of circuits “And through the corresponding third group of inverters — with the first inputs of the corresponding fourth group of circuits; the outputs of each of the fourth group of circuits,” And are connected to the second inputs of one of the third n of one of the fourth groups of circuits “And, connected with the subsequent output detection of permitted interrupts, the first output of which is connected to the corresponding input of the encoder and through the corresponding inverter of the third group of inverters to the second inputs of one of the third and one of the fourth g An AND circuit connected to the subsequent output of the detected interrupt detection circuit, the last output of which is connected to the first input of the corresponding AND circuit of the third AND circuit, the second input of which is connected to the output of one of the fourth group of the AND circuit with the previous output of the detected interrupt detection scheme; the outputs of the third group of circuits "And connected to the inputs of the encoder, the outputs of which are connected to the outputs of the device.