SU435596A1 - DUO FREQUENCY FREQUENCY PROOF - Google Patents

Description

The invention relates to radio engineering. The frequency doubler will be used in frequency synthesizers, radio receivers, etc.

In the above devices, it is necessary to multiply the filling frequency of ko.RTIKh of radio radios and pulsations, and the frequency of filling can vary widely (for example, in frequency synthesizers, the maximum possible frequency is 1: 2 or 1: 3).

In the known frequency doubler, which contains an input signal converter, the outputs of which are connected through an integrator to an adder, the input signal is converted into two antiphase square signals, which in the integrators turn into triangular pulses. In limiters, these pulses are limited, with the result that at their outputs the duration of the emuls depends on the frequency of the input signal. The signal that passes through the logic adder acts on the output driver block, which creates oscillations at twice the frequency. The threshold device and the control element automatically set the limit thresholds in the limiters.

Due to the presence of peppeal feedback feedback, this device has a large

settling time and cannot multiply the carrier frequency of short radio pulses.

The purpose of the invention is to accelerate the establishment of the output frequency - in that the proposed frequency doubler introduces a comparison circuit, two inverters and two coincidence circuits, the inverter outputs being connected to the inputs of the comparison circuit whose output is connected to the input of the second coincidence circuit and through the first inverter with the input of the first matching circuit, and one of the outputs of the input signal generator - with the input of the second matching circuit and through the second inverter - with (INPUT of the first circuit coincides: M | IL. The outputs of the matching keys to ummatoru.

The block diagram of the device shown in the drawing.

The frequency doubler contains an input signal converter 1, integrators 2 and 3, a circuit compared to 4, converters 5 and 6, a matching circuit 7 to 8, an adder 9.

The input signal converter / contains an amplifier stage with a pulse M transformer and two stages of threshold devices. Two sequences of rectangular pulses taken from the windings of a transformer with a grounded midpoint are fed to threshold devices. From the exit

The first noporvOBoro device is removed right before the end, and from the output of the second threshold device - a sequence of 0.5 pa relative to the input. The special feature of such a formation is that when there is no input voltage signal and the outputs of the threshold devices, o.

With the integrators 2 and 3, the sawtooth voltage is applied to the comparison circuit 4, which is quite sensitive, i.e., the f / cpao C saw.

In the comparison circuit, a new sequence of rectangular pulses is formed, shifted relative to the input by / 4 T.

The front and rear fronts of such imiuls are located at the point corresponding to the equality of the two sawtooth stresses. When the selection requirements of the / C-chains are met, the intersection point, i.e., the point corresponding to the equality of the voltages, is in the middle of the gp-shaped voltage and does not depend on the input multiplied frequency.

By using inverters and coincidence circuits, two sequences of pulses are obtained, after which they are combined, a sitnal is formed at a frequency equal to twice the frequency of the input signal.

Thus,% 1, at the doubler output, there are only even harmonics of the multiplied frequency. A multiplier consisting of n such doublers multiplies 2 / times. The settling time depends on the phase of the high frequency oscillation. It lies in the range from 0.5 to 7 and depends little on the number of doublers.

Subject invention

A frequency doubler containing an input signal converter, the outputs of which are connected via an integrator to an adder, characterized in that, in order to accelerate the establishment of the output frequency, a comparison circuit, two inverters and two coincidence circuits are introduced, and the integrator outputs are connected to the inputs of a comparison circuit. the output of which is connected to the input of the second matching circuit and through the first inverter to the input of the first matching circuit, and one of the outputs of the input converter to the input of the second matching circuit and through Torah inverter - to the input of the first coincidence circuit, wherein the outputs of coincidence circuits connected to the adder.

5 | E- L.J