SU1429316A1 - Pulse recurrence rate multiplier - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation, radio engineering and communication systems. The aim of the invention is to reduce the setting time of the output frequency due to coarse tuning. The device contains a pulse generator 1, a counting frequency block 2, a phase detector 3, elements 4-6, a reversible counter 7, a voltage-code converter 8, triggers 9 and 10, an input bus 11, an output bus 12, to achieve In this case, an OR 13 element is additionally introduced into the device, the first input of which is connected to the inverse output of the second trigger 10, the second input is connected to the fourth output of the phase detector 3, and the code to the second input of the first element. And 4. When synchronizing, the triggers switch state 1 providing a precise adjustment of the generated pulses by the ring of the phase-locked frequency converter with respect to the pulses arriving at the input 11 of the device. 2 Il (L with:

Description

; The invention relates to pulsed TtexHHKe and can be used in Ivomatics, radio engineering and communications equipment systems.

The circuit of the invention is a reduction in the time for setting the output frequency $ a through a coarse tuning. FIG. 1 shows the structure-: electrical device diagram; on pig 2 - timing diagrams for the device operation.

The device contains a 1 "pulse generator, a scaling unit 2 frequencies, a phase detector 3, the first second and third elements AND 4-6, a reversive {counter} 7, a transducer 8; code-voltage, the first D-flip-flop 9 1i the second D-flip-flop 10, C-input of which is iporo with one with the input bus 11

| device and the first input of the phase detector, the second input of which is connected | DININEN with the output of the frequency converter 2 frequency and the C input of the first D-flip-flop 9, the input of which is connected to you. the pulse generator 1 and the input of the frequency converter 2, the R input with a ground bus, the D input with the first input of the phase detector 3, and the inverse output with the R input of the second D trigger 10, the D input of which is connected to the second output of the phase detector}, - the direct output - with the second input, the second element I 5, the output of which is connected to the output bus 12 of the device. The output of the first element And 4 is connected to the summing input of the reversible counter 7, the outputs of which are connected to the inputs of the converter

8 code-voltage whose output is coq

dinene with control input of pulse generator 1. The output of the latter is connected to the input of the frequency converter block 2, the second input of the second ele

ment And 5 and the first inputs of the first 4

and the third 6 elements And, the second input of the latter is connected to the third output of the phase detector, and the third input - to the first input of the second element And 5.

In addition, the device contains the element OR 13, the first input of which is connected to the inverse output of the second D-flip-flop 10, the second input - to the fourth; the output of the phase detector 3, and the output - to the second input of the first element And 4, while the output of the third element AND 6 is connected to the input of the subtraction, reversible counter 7.

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The device works in the following way.

In the initial state, the required multiplication factor is entered into the scaling unit 2. The minimum and maximum values of the code of the reversible counter 7 correspond to the minimum and maximum pulse frequency of the generator 1, respectively, and are equal to the pickup band of the PLL.

In synchronous mode, i.e. when the pulses at the inputs of the phase detector 3 are alternately received (modes 1 and II in Fig. 2), the device operates as follows.

Let the input frequency pulse appear at the first input of the phase detector 3, then the trigger 14 switches to state 1 and the pulse from the output of block 2 that turns on the second input switches the trigger 14 to state O. The pulse from the direct output of trigger 14 goes to the first input of the Element OR 13 and from its output to the second input of the element AND 4, thereby ensuring the passage of pulses from the output of the generator 1 to the input of the summing of the reversible counters 7. The signals from the output of the last arrive at the converter 8, its output voltage increases, which leads to an increase in the pulse frequency generated by the oscillator {1 1. The next pulse from the output of block 2 appears earlier than in the previous case, which leads to a decrease in the phase difference of the compared frequencies. This process continues until the phase difference of the compared frequencies is zero.

If a pulse from the output of block 2 appears at the second input of the phase detector 3, earlier than the pulse at its first input, the trigger 15 switches to state 1 and generates a pulse at the forward output, which goes to the second input of the AND element and if there is the voltage at the forward output of the trigger 10 provides for the passage of pulses from the output of the generator 1 to the input of the inverter counter 7. In the synchronous mode of the PLL D-triggers 9 and 10 is in state 1, providing the presence of voltage at the third and second inputs, respectively And 5 and 6. Signals from the output of the reversible counter 7 are fed to the converter 8, its output voltage decreases, which leads to a decrease in the pulse frequency of the generator 1. These cycles are repeated until the phase difference of the compared frequencies is zero. , at the same time the formed sequence of pulses by the generator 1 through the element 5 is fed to the output bus 12 of the device.

When the synchronization fails (modes III and IV in Fig. 2), coarse tuning elements are turned on, for example, C-input of the trigger 14 receives two more pulses from the input 11 of the device. Then the triggers 14 and 10 are switched under the influence of the second pulse to the state O and there are no pulses at the output of the elements 5 and 6, and the voltage on the inverse output of the trigger 10 provides the voltage through the element OR 13 at the second input of the element 4 regardless of the state of the fourth output of the phase detector 3, which leads to the appearance of pulses generated by the generator 1 at the input of the summation of the active counter 7, thereby increasing the frequency of the pulses of the generator 1 until the synchronization to PLL prints, then triggers 14 and 10 are switched to state 1, and the device goes into phase shift mode.

If the synchronization cycle does not occur during the cycle in question, eventually the overflow counter 7 overflows and it switches

with the zero state, as a result

which, the pulse frequency from the output of the generator 1 decreases to a minimum, and as the next pulses arrive at the summing input of the reversible counter 7, the pulse frequency of the generator 1 increases again until the synchronization of the PLL ring. During synchronization, the triggers 4 and 10 switch to state 1, providing accurate adjustment of the phase of the generated pulses by the generator 1 through the elements 4 and 6 and the appearance of these pulses at the output of the element 5. The operation of the device in this mode is similar to that described.

In case of synchronization failure, when the C-input of the trigger 15 is received under

A series of two pulses from the output of the scaling unit 2, the triggers 15, 9 and 10 are switched under the influence of the second pulse to the state O and the operation of the coarse tuning elements is carried out in the same way as in the previous case. During synchronization, the triggers 15, 9, and 10 are switched to state 1, thereby ensuring the fine adjustment of the phase of the generated pulses by the PLL, relative to the pulses fed to the input 11 of the device.

Fo, rmula invention

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The multiplier of the pulse repetition frequency, containing a pulse generator, the output of which is connected to the input of the counting unit and the first inputs of the first, second and third elements I, the output of the last of which is connected to the output bus, the second input to the direct output of the first trigger, information, the input of which is connected to the first output of the phase detector, the first input of which is connected to the input bus and the clock input of the first trigger, the input reset of which is connected to the inverse output of the second trigger, information input which is connected to the second output of the fs. detector, the second input of which is connected to the output of the counting unit and the clock input of the second trigger, the reset input of which is connected to the common bus, a reversible pulse counter, the inputs of summation and output are connected to the outputs of the first and the second element And, the outputs are parallel to the converter inputs; the code is the voltage, the output of which is connected to the input of the pulse generator, characterized in that, in order to reduce the time to enter the mode,

an OR element is entered, the output of which is connected to the second input of the first

element I, the first input with the inverse output of the first trigger, the second input with the third output of the phase detector, the fourth output of which is connected to the second input of the second element I, the third input of which is connected to the direct output of the first trigger.

Claims (1)

Claim A pulse repetition frequency multiplier comprising a pulse generator, the output of which is connected to the input of the conversion unit and to the first inputs of the first, second, and third AND elements, the output of the last of which is connected to the output bus, the main input is with the direct output of the first trigger, information /) the input of which is connected to the first output of the phase detector, the first input of which is connected to the input bus and the clock input of the first trigger, the reset input of which is connected to the inverse output of the second trigger, the information input of which it is connected to the second output of the phase detector, the second input of which is connected to the output of the conversion unit and the clock input of the second trigger, the reset input of which is connected to a common bus, a reversible pulse counter, the summing and subtracting inputs of which are connected to the outputs of the first and second elements outputs - bitwise with the inputs of the converter code - voltage, the output of which is connected to the input of the pulse generator, characterized in that, in order to reduce the time to enter the mode, an OR element is inserted into it, turn is connected to the second input of the first AND gate, a first input - with an inverted output of the first flip-flop, the second input - to a third phase detector output, a fourth output is connected to the second input of the second AND gate, a third input coupled to a direct output of the first flip-flop. Figl with