SU432494A1 - POSSIBLE-PERFORMANCE DEVICE - Google Patents

Description

one

The invention relates to the field of automation and computer technology and can be used to create devices that allow to obtain the ratio, product and the sum of frequencies.

A device for dividing frequencies is known, which contains a binary counter, two AND circuits, two triggers, the first inputs of the AND circuits being connected to the sources of pulse frequency signals. The output of the first circuit "And connected to the counting input of the binary counter and the input of the installation in the" unit of the first trigger. The output of the overflow signal of the counter is connected to the input of setting to "zero of both triggers. A single output of the first trigger is connected to the second input of the “I. A single output of the second trigger is connected to the second input of the first circuit “I. The zero output of the second trigger is connected to the output of the device.

However, such a device allows only the operation of dividing two frequencies arriving simultaneously.

The aim of the invention is to expand the functionality of the device, which, in addition to the above operation, implements various functional dependencies with frequencies in the form of combinations of multiplication, division and addition of frequencies while preserving the result and presenting the result of the operations in binary code. Frequencies can be posted at different times or simultaneously.

The goal is achieved by those. that the device contains a delay line, a group of valves, an additional binary counter, the counting input of which is connected to the output of the second “I. The zero outputs of the bits of the additional counter are connected to the first waves.

valves, the second inputs of these valves are connected to the output of the delay line, the input of which is connected with the output of the main counter overflow signal. The outputs of the valves are connected to the single inputs of the bits of the main counter, the single outputs of the bits of the additional counter are connected to the outputs of the device. The input of zeroing the additional counter, the input of the entry of the binary code into the main counter and the input of the installation into

“The unit of the second trigger is connected to the inputs of the device.

The drawing shows the block diagram of the device. It contains input 1 from the first source

pulse frequency signal, input 2 from the second frequency pulse signal source, unit outputs 3 bits of the additional binary counter 4, input 5 of setting the second trigger 6 to the unit, primary binary counter 7, first trigger 8, first AND 9 circuit, second The circuit “No. 10, inputs 11 of entering the binary code into the main counter 7, input 12 zeroing the additional counter 4, delay line 13, zero output 14 of the second trigger 6 and the valve group 15. The device works as follows. In the initial position, the counters 7 and 4 and the triggers 6 and 8 are set to the state "O" (the installation inputs of the device return to the outgoing state, except for the zero-reset input 12 of the additional counter, and the drawing is not shown). In the device preparation mode for operation in counter 7, by inputs And write the mass coefficient K in the inverse binary code and start the device, giving the signal to input 5, which sets trigger 6 to the state "1. The trigger 6 opens the AND 9 circuit, which transmits the frequency pulses FZ to the counting input of the counter 7, to the PA trigger 8, to set it to the state "1. Trigger 8 opens an AND 10 circuit that transmits FI frequency pulses to the counting input of counter 4. Both flip-flops 6 and 8 are set to "On the overflow pulse of counter 7, stopping the passage of frequencies FI and FZ to counters 7 and 14. From trigger output 14 6, a high potential is indicated indicating the end of the operation. The duration of the TSP gate, generated by counter 7, when counting pulses of the frequency FZ with a period TZ, will be: h,. K- - The number of frequency pulses FI, counted by the counter 4, is: N, K-. Thus, the device performs parallel conversion of a pair of frequencies fi and FZ into an NI binary code proportional to the ratio of these frequencies, while preserving the result of the operation in counter 4, which is rewritten into counter 7 as an inverse binary code through a group of valves 15 with counter overflow pulse 7 delayed the delay line 13. Presetting the counter 4 to the initial state on input 12, applying FS to Fi to inputs 1 and 2, restarting the device on input 5, receive a parallel conversion of the second pair Frequencies Fa and 4 in their relationship and multiplying the ratio by the result of the previous operation: N, N, K.4 A necessary condition for performing operations (1), (2) and (3) is the simultaneous presence of frequency pairs (Fi / Fz),. .., (FnfFn + i), whereas with respect to each other, frequency bunks may be present simultaneously or at different times. All other operations with frequencies are performed by the device sequentially, receiving and processing each frequency separately, and the frequencies can exist both simultaneously and at different times. The device still combines the operation of frequency conversion into a code and the operation of dividing or multiplying or adding it with the result of the previous operation. These operations are carried out by replacing the frequency of the dividend or divider with a known DFR frequency, i.e. connecting the fon frequency to the corresponding input 1 or 2 of the device instead of the unknown frequency. So, when replacing operation (2) FZ with FQJJ, we get the frequency conversion operation .FI into the code: N mF, where t - and replacements when performing operation (3) FZ, 4, Fe, ... na Fon, receive operation multiplying frequencies: N CF, .F. .F, -F- ,, ..., (5) where C n is the number of unknown frequencies involved in the operation. The operation of adding frequencies is performed by repeatedly performing operation (4), sequencing it with restoring the scale factor K. After each repetition. In this case, the resetting of the counter 4 to the initial state after each operation is not performed: L m (f,..., + Fn) (6) The device can also perform various functional dependencies with frequencies in the form of combinations of the operations described above. The subject of the invention is a multiplying-separating device containing a binary counter, two I and V trigger circuits, the first inputs of the AND circuits are connected to sources of pulse frequency signals, the output of the first AND circuit is connected to the counting input of the binary counter and to the installation input of the unit of the first rigger, the output of the overflow signal of the counter is connected to the inputs of the installation to "zero active triggers, the unit output of the first rigger is connected to the second input of the second branch" And, the single output of the second trigger is connected to the second input of the first The second AND circuit and the zero output of the second trigger are connected to the output of the device, characterized in that, in order to expand the functionality, it contains a delay line, a valve group, a secondary binary counter, the counting input of which is connected to the output of the second AND circuit, zero outputs of the The additional inputs of the counter are connected to the first inputs of the gates, the second inputs of these gates are connected to the output of the delay line, the input of which is connected to

the output of the overflow signal of the main counter, the outputs of the valves are connected to the single inputs of the bits of the main counter, the single outputs of the bits of the additional counter are connected to the outputs of the device, the zero input of the additional counter, the inputs of the binary code to the main counter and the input of the unit of the second trigger are connected to device inputs.