SU1483464A1 - Computer - Google Patents

Abstract

This invention relates to automation and computing. The purpose of the invention is to expand the functionality by performing addition and subtraction and expanding the field of application of the device. The computing device contains three AND 2 elements, a pulse generator, two counters, a sum and difference calculating unit, four switches, three registers 15, and two flip-flops. The device converts the duration of the input time-pulse signals into a unit-position code with subsequent processing. The device performs multiply-long and summing-subtracting operations and allows you to process pulses both at the same time and at different points in time, which expands the functionality of the device and its application area. 1 hp f-ly, 4 ill.

Description

The invention relates to automation and computing and can be used in information-measuring systems for building specialized computing devices with a pulsed form of information representation.

The purpose of the invention is to expand the functionality by performing addition and subtraction operations and expanding the scope.

Figure 1 presents the block diagram of the computing device; 2 is a functional block diagram for calculating the sum and difference; FIG. 3 is a functional diagram of the first, second and fourth switches; figure 4 is a functional diagram of the third switch.

The computing device contains the first - the third elements AND 1 - 3, the generator 4 pulses, the first and second counters 5 and 6, and the counting input 7 of the first counter 5 is connected to the output of the element I 1, whose inputs are connected to the input 8 of the first time of the pulse signal device and to the output of the generator 4 pulses, block 9 calculating the sum and difference, the first - the fourth switches 10-13, the first - the third registers 14-16 and the first and second triggers 17 and 18. In addition, in figure 1 are marked: 19 and 20 - per. VA and the second group of information inputs of the switch 10; 21 - the first group of inputs of the block 9j 22 - the counting input of the counter 6j 23 and 24 - the first and second groups of information 4

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05ъ 05 4Ь

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Dov switch 11; 25 - the second group of inputs of block 9} 26 and 27 - outputs of the codes of the sum and difference of block 9, respectively; 28 and 29 - the first and second groups of information inputs of the switch 12} 30 and 31 - the first and second groups of information inputs of the switch 13; 32 —the device 33 outputs — the second pulse time input of the device 34 and 35 — installation inputs into 1 flip-flops 17 and 18} 36 and 37 — the first and second control inputs of the switch 12; 38 and 39 — the first and second inputs set the operation code of the device} 40 — register read resolution inputs} 41 — the control inputs of the switches 10 ,. 11 and 13; 42 — device zeroing input} 43 and 44 — inputs for zeroing of counters 5 and 6j 45 and 46 — inputs for zeroing of triggers 17 and 18.

Block 9 for calculating the sum and difference (Fig. 2) contains n groups of n elements And 47 (1, 47, ... 47, ..., 47 h (where i is the element number, j is the group number) and two groups of (p-1)

elements OR 48 and 49.

/

The first, second and fourth switches 10, 11, 13 contain the group of elements AND 50 and the group of elements OR 51, the third switch 12 contains the element NOT 52, the first and second elements And 53, 54 and the element OR 55,

The device works as follows.

At the initial moment of time, at the input 42 zeroes, O is present, which has no effect on the operation of the device. The second input 39 of the operation task is also supplied with O, which is fed to the inputs 40 of registers 14-16 and the inputs 41 of switches 10, 11, 13. The first input 38 of the operation task is fed to the second control input 37 of the third switch 12.

The first and second inputs 8.33 of the device are pulsed, having a duration corresponding to the time intervals T1 and T l, the ratio of which is required to be calculated. Pulses of exemplary frequency from the output of the generator 4 pass through the first and second elements AND 1.2 during the time intervals T 1 and Tg to the counting inputs 7.44 of the first and second counters 5,6. The number of pulses received at the counters 5.6 during

g 0

five

0

Q,

five

0

five

time slots T 1 and Tr are represented in them in a unit position code, i.e. an excited one bit of the counter corresponds to the weight of the number. These code values are then kept unchanged in counters 5.6 throughout the entire measurement time. At the outputs of the trigger 17,18, O are always present. At the end of the time intervals, 1 appears on them, i.e. both flip-flops 17, 18 go into one state on the falling edge of the time interval and remember it.

Signals 1 are fed to the inputs of the third element And 3, from the output of which is fed to the first control input 36 of the third switch 12.

Codes from the outputs of the counters 5,6 are fed to the inputs of the first and second registers 14,15 and the first inputs 19, 23 of the first and second switches 10, 11.

At the outputs of the first and second counters there are unit position codes of the numbers A and B, corresponding to the duration of the input pulses. Accordingly, the outputs of the first and second switch 10, P will contain unit position codes of the numbers A and B or logA and logB, depending from the control signals at the control inputs 40 and 41. These codes are received respectively on the first and second inputs 21 and 25 of the sum calculation unit 9. Since control inputs 40, 41 of registers 14-16 and switches 10, 11, 13. are O, there are codes from the outputs of the first and second registers 14, 15 on the outputs of the first and second switches 10, 11. the second inputs 20, 24 of the switches 10, 11.

At the outputs 27 of the sum calculation block 9, the code of the difference between the input codes appears (for our example log A - - log B log A / B). The code from the outputs 27 goes to the second inputs 29 of the third switch 12 and appears at its outputs, arriving at the inputs of the third register 16 and the first inputs 30 of the fourth switch 13,

In accordance with the code at the inputs 40 and 41 of the third register 16 and the fourth switch 13, the code from the first inputs 30 of the fourth switch 13 is not

arrives at its outputs 32. The A / B code already converted by the third register 16, arrives at the second inputs 31 of the fourth switch 13 and enters at its outputs 32, which corresponds to the ratio of the durations of the time intervals.

To multiply the intervals T. and T, the input 38 of the device is supplied 1. Accordingly, the code will be generated at the outputs 26 of the sum calculation unit 9 and fed to the first inputs 28. of the third switch 12 and its outputs, since at its second control input 37 present 1. The code will correspond to log AxB logA + LogB and be converted in the third register 16 to the corresponding unit position code AxB ,. which through the fourth switch 13 enters the outputs 32 of the device.

To add time slots to the first and second inputs 38, 39 set 10

Thus, it is obvious that about the time interval can arrive at different times.

The sum calculation unit 9 (FIG. 2 works as follows.

On the first and second inputs 21,25 step unit-position codes ie one of each inputs 21, 25 enters 1.

At the output of the element AND 47i, j, on both inputs of which there is 1, 1 appears, which is placed on one of the inputs of one of the first 15 outlets and from the second elements OR 48.4 at the outputs of which appear 1, arriving at one of the outputs 26, block 9.

Thus, the device allows not only to calculate the ratio and the product of time intervals, but also parallelization and subtraction, and in the device time intervals can be

20

1, which is disabled not only simultaneously, but registers 14-16, i.e. O will be present at their outputs. Therefore, the codes of both counters 5,6 are not converted to logarithmic codes. A direct addition of 30 both A and B values is performed. The result of adding from the first outputs 26 through the third and fourth switches 12, -13 goes to the outputs 32 devices.

at different times

Formula of invention

1. A computing device with two holding counters, the first of which are connected by a counting input to the first element I connected by a first input to the input of the first time of a pulse signal of the device with a setup input of 1 trigger, and the second input to the output of a pulse generator and the first input of the second element And connected by the second input to the input of the second time pulse signal of the device, and the output To the counting input of the second counter, and the trigger output is connected to the fifth input of the third element And, due to the fact that expanding the functional possibilities by performing the operations of adding and subtracting and expanding the field of application of the device, the sum and difference calculator, four commutators, three registers and the second transducer connected by a setup input to the second time input pulse are added. the signal of the device, the entrance of the laziness - to the input of the zeroing device and the input of the zeroing of the first trigger and counters, and the output to the second input of the third element I, while

To subtract time intervals

1 is fed to the input 39 of the device, and O is fed to the input 38. In this mode, as in the previous one, the conversion to logarithms does not occur, but the A and B codes are directly subtracted, the result of which from the outputs 27 of the sum calculation unit 9 The third and fourth switches 12, 13 enter the outputs 32 of the device.

triggerge

The zeroing of the counters 5.6 and ditch 17, 18 occurs by applying to zero input 42, which is fed to the inputs 43, 44, 45 and 46, respectively, of the first and second counters 5.6 and the first and second triggers 17.18. The calculation is carried out only after occurrence 1 at the output of the third element And 3, and this is possible after the triggering of both triggers 17,18, which are triggered at the end of time intervals.

0

Thus, it is obvious that both time slots may arrive at different times.

The sum calculation unit 9 (FIG. 2) operates as follows.

The first and second inputs 21,25 receive unit position codes, i.e. one of each inputs 21, 25 enters 1.

At the output of the element AND 47i, j, at both inputs of which there is 1, 1 appears, which is fed to one of the inputs of one of the first and from the second elements OR 48,49, at the outputs of which 1 appears at one of the outputs of 26.27 block 9.

Thus, the device allows not only calculating the ratio and the product of time intervals, but also parallel addition and subtraction, and in the device time intervals can be supplied

not only at the same time, but

at different times

Formula of invention

Claims (2)

1. A computing device containing two counters, the first of which is connected by a counting input to the output of the first element I connected by the first input to the input of the first time pulse signal of the device and the installation input to 1 trigger, and the second input to the output of the pulse generator and the first the input of the second element I, connected by the second input to the input of the second time of the pulse signal of the device, and the output to the counting input of the second counter, with the trigger output connected to the first input of the third element I, which is that, in order to expand the functionality by performing operations of adding and subtracting and expanding the field of application of the device, it additionally introduces a sum and difference calculating unit, four switches, three registers and a second trigger connected by a setup input to the second input a pulse time signal of the device, the input of the safety switch - to the input of the device zeroing and the input of the zeroing of the first trigger and counters, and the output to the second input of the third element I, while the outputs of the bits of the first counter are connected to the information inputs of the first register and the first group of information inputs of the first switch connected by the second group of information inputs to the outputs of the first register, and the outputs to the first group of inputs of the sum and difference calculator connected to the second group of inputs and outputs the second switch connected by the first group of information inputs to the outputs of the bits of the second counter and the information inputs of the second register, while the outputs of the sum and difference codes are The calculation of the sum and difference is connected to the first and second groups of information inputs of the third switch, respectively, the first control input of which is connected to the output of the third element I, the second control input to the first input of the device operation code, and the outputs to the information inputs of the third register and the first group of information inputs of the fourth switch connected to the second group of information inputs with the outputs of the third register, the control input - with the second input of the operation code set by the device -keeping, with the control inputs of the first and second switches vtrro and read enable input of the first, second and third registers, and output - with output ustroystva4 2. The device according to claim 1, that is, so that the block for calculating the sum and difference contains n groups of n elements And two groups of (n-1) OR elements, each i- the first element of the jth group of elements (, n, ..., n) is connected by the first input to the ith input of the first group of inputs of the sum and difference calculating unit, and the second input to the jth input of the second group of inputs of the sum and difference calculating unit , the output of the first element And the first group is connected to the output of the n-th digit of the difference code of the sum and difference calculating unit, the output of the n-th element And of the first group is connected to In the course of the first digit of the sum code of the sum and difference calculation unit, each Kth element OR of the first group (, n-1) is connected to the BBIXO house with the output of the (K – H) th digit of the sum code of the sum and difference calculation unit, and inputs - with outputs (n + j- -K-1) -x elements AND each j-th group (ja1, K + 1), each K-th element OR of the second group is connected to the output of the K-th bit of the difference code the block for calculating the sum and difference, and the inputs to the outputs (nj - K + 2) -x elements AND of each j-th group (, n-К + 1), s with: l wvesvi 27 / t27 -t 27p 27 27