SU296053A1 - DIGITAL PHASOMETER FOR MEASURING THE IMMEDIATE VALUE OF PHASE SHEAR - Google Patents

Description

The invention relates to the field of phase-measuring technology.

Known phase meters measuring instantaneous phase shift, containing pulse drivers, electronic switches, an exemplary frequency generator, a reversible counter, a control unit, a trigger, a frequency divider and a recording counter, do not provide a direct reading of the phase shift in degrees, and also have a relatively low speed .

The proposed phase meter allows you to get a direct readout and increase speed due to the fact that it is equipped with a scheme for determining the relationship of time intervals, built on a binary counter for phase shift pulses, a binary counter for period pulses, a common binary counter for pulses, two blocks of coincidence circuits, and two schemes "OR, the input of the registering counter is connected via the first OR circuit to the output of the first block of coincidence circuits, the control inputs of which are connected to a binary pulse counter MOTOR PHASE, its signal inputs - the total binary pulse counter, to which are connected parallel to the signal inputs of the second unit of the coincidence circuits and the control inputs of the block are connected to the binary counter pulse periods, the output

the second block of coincidence circuits through the second circuit OR is connected to the frequency divider, and the control unit is connected to the control input of the circuit I.

The drawing shows the block diagram of the proposed phase meter.

The device operation is based on measuring the time interval between adjacent zero crossings of two investigated voltages.

within one period, the phase shift between which should be measured, with the subsequent automatic conversion of the measurement result of this run-through into a digital readout, presented directly in

phase angle measurement units (e.g., in degrees).

The phase meter contains drivers 1 2 control pulses from the input signals Ll and t / 2, key 3, control key 4, circuit

“And 5, generator 6 of exemplary frequency, common binary counter 7 pulses, binary counter 8 pulses of phase shift, binary counter 9 period pulses, two blocks 10 and // coincidence circuits, schemes“ OR 12, 13, divider 14 frequencies by 360, registering (digital) counter 15 pulses, control unit 16.

from the input signals 6i and bz, at the moments when the instantaneous values of the voltage Ui and 1/2 pass through zero, control pulses are emitted which open the key 3 for a time, which is proportional to the measured phase shift. At the same time, the control pulses from the driver 2 unlock key 4 for the duration of the period TX of the input voltage U2. After that, the keys 3, 4 are closed by a signal from the control unit 16 to the time of the second measurement cycle, during which the automatic conversion of the measurement result of the time interval t to a digital readout, presented directly in units of the phase angle, occurs.

The gap is measured by filling it with quantizing impulses from a generator of exemplary frequency through a public key 3, the number of which is counted by a binary counter 8 of phase shift pulses, and measuring the period Tx of an input signal by filling it with quantizing pulses from a generator 6 of exemplary frequency using an open control key 4, the number of which is counted by a binary counter 9 period pulses.

The number of pulses N-. counted by a binary counter 8 phase shift pulses.

L.

where TQ-period of quantizing pulses.

The number of pulses NT, calculated by the binary counter 9 pulse period.

 t

N,

In the second cycle, from block 16 of control, one of the inputs of the circuit "AND 5 receives a signal. At the same time, quantizing pulses from the generator

6 sample frequency received in a common binary counter 7 pulses.

The output levels of the trigger bits of binary counter counters 8 and 9 9 control the potential inputs of blocks 10 to. 11 coincidence circuits. The outputs of the triggers of the bits of the common binary counter 7 pulses are fed to the pulse inputs of these same matching circuits. When both signals coincide at the inputs of the coincidence circuit, signals appear that pass through the circuit OR 12 to the digital counter 15 pulses and through the circuit OR 13 to the frequency divider 14. The states of the matching circuits and, therefore, the total frequency at the output of the matching circuit blocks 10 and // set the trigger states of binary counters 7, 8 and 9. For example, the triggers of the most significant binary bits of the binary counters 8, 9 control the coincidence circuits signals from the youngest trigger of a common binary counter

Nr

fr

(3)

UL

where is the number capacity of counters 7, 8, 9.

Taking into account the expression (2), we get

/ g - (4)

Goch

That tona

Ummarna frequency output circuit "OR

N.

(five)

TnN :,

Taking into account the expression (1), we get

  Goch

(6)

When entering the divider 14 360 pulses of the total frequency fj. an overflow pulse is emitted to the control unit 16, which removes the signal from one of the inputs of the "AND 5" circuit. The "And was open for the time

l .

The number of counted pulses in a digital counter 15 pulses

„L A / - / .. (8)

Taking into account the expression (4), (6), (7), we get

L,

 X

That is, the number will be equal directly to the phase shift in degrees.

Subject invention

A digital phase meter for measuring an instantaneous phase shift value comprising a control unit and a phase shift converter in a time interval, made in the form of pulse shapers, electronic key, reference frequency generator, frequency divider and recording counter, characterized in that to provide a direct reading and increase the speed, the phase meter is equipped with a scheme for determining the relationship of time intervals, built on a binary counter pulse phase shift, a binary counter pulse in a period, a common binary pulse counter, two blocks of coincidence circuits, and two circuits

"OR, while the input of the registering counter through the first circuit" OR is connected to the output of the first block of coincidence circuits, the control inputs of which are connected to the binary counter of phase shift pulses, its

signal inputs - to a common binary pulse counter, to which the signal inputs of the second block of coincidence circuits are connected in parallel, and the control inputs of this block are connected to a binary counter im34

the coincidence circuits through the second OR circuit are connected to the control input connected to the frequency divider, and the I.I.

296053

and,