SU1762298A1 - Programmable timing device - Google Patents

Abstract

The invention relates to computing and automation, in particular to automatic control devices, where the inclusion of various mechanisms in a certain sequence in time is required, and can be used to control technological processes. The aim of the invention is to expand the scope due to autonomy when issuing commands, the time of their occurrence and the formation of the duration and improving the accuracy of issuing all commands relative to the start of operation signal. The device contains a pulse generator 1, an address register 2, a memory unit 3, a trigger 4, a pulse counter 5, a comparison element 6, a first 7 and a second 8 group of switches, elements OR 9-13, a signal conditioner 14, a sampling resolution, an inverter 15 , element 16, three delay elements 17, 19, 20, blocking trigger 18, output register 21 on D-triggers, group 221 ... 22N of galvanic isolation elements, line 23 data address, bus 24 control commands. 9-2-10-14-11-3-8--21-22. 4- 1-5-6-16-17-20-13-18-16, 20-12-2-3. 4- 15-7-3, 17-19-21.4 Il. WITH

Description

The invention relates to computer technology and automation, in particular, to automatic control devices, where the inclusion of various mechanisms in a certain sequential body is required. and it can be a zerplzovand to control technological processes &

69MI.

A software temporary device is known that contains a pulse generator and a pulse counter connected in series, a program block block, a decoder, AND elements, an additional AND element, an unbalanced trigger, and actuators.

In order to increase the reliability of the device and to ensure the possibility of automatically stopping the device in the drp@nne.ln program, the device has OR elements, wi-fi element I, t-datyik modes, a pulsator, and a symmetric trigger.

The disadvantages of these devices are: the constant duration of the commands issued, the lack of accuracy of the commands issued, the low memory utilization rate, the operational ability to change the duration, the issuance time and the number of commands.

Of the known ones, the closest in technical essence to the claimed is a software control device containing a pulse generator, a counter, a first and second decoder, a memory unit, a first and second group of decoders, a trigger, an AND element, an address register, an output register , delay element, group of multiplexers, group of decoders.

The disadvantages of the known device, selected as a prototype, are:

- limited functional capabilities, in particular, it cannot provide the autonomous issuance of more than one command, the codes of which are recorded in the memory unit; in order to issue all the commands, the control unit is additionally necessary;

- the control unit only asynchronous commands can initiate the device to issue subsequent commands;

- the issued commands have a constant duration, and the time of their issuance must be additionally determined by the control unit;

-the control unit asynchronously initiates the device to issue commands, which reduces the accuracy of their issuance relative to the original signal sign of the beginning of work.

The aim of the invention is to expand the functionality due to autonomy when issuing commands, the time of their occurrence and formation over the duration and improving the accuracy of issuing all commands relative to the signal sign of the start of work.

The goal is achieved by the fact that a software temporary device containing a pulse generator, an address register, a random access memory (RAM) block, a trigger trigger, a pulse counter, the first and second switch groups, the first And element, the first delay element, and the output register , the comparison element is additionally introduced; the first, second, third, fourth, and fifth OR elements, the signal conditioner, sampling resolution, inverter, blocking trigger, the second and third delay elements, the output register is made on D-triggers, and Op pulses is connected in series a reference frequency generator, a second AND gate and a frequency divider, wherein the group of information lo- rows register address and group of information inputs of the first group of switches connected to the backbone

address data. The control input of the address register is connected to the control command bus, the address record, the outputs of the address register are connected to the group of information inputs of the RAM block, the group of outputs of the switches of the second group is connected to the first group of inputs of the comparison element, the second group of inputs of which are connected to the bit outputs of the pulse counter , the counting input of which is connected to the output of the frequency divider of the pulse generator and to the first input of the first element OR, and the installation input of the pulse counter, the first inputs of the second and t The other OR elements, reset trigger trigger inputs, frequency divider and output register D-flip-flops are connected to the reset control command bus, start trigger recording entry and the second inputs of the fourth and third OR element are started sign, and the trigger trigger output is connected to the first permitting input of the first element I, to the control input of the main memory unit and to the second input of the switches of the second group and through the inverter to the control input of the switches of the first group whose outputs from Connected with a group of I / O blocks of the operating memory of the switches of the second group of information inputs, the first input of the second element l / PI is connected to the control command bus, the exchange of its output to the input is reset of the address register, the output of the comparison element is connected to the first input of the second element And output which, through the first and second delay elements, is connected to the first input of the third OR element, the output of which is connected to the input, resetting the lock trigger, the inverse output of which is connected to the second enabling input of the first About the And element, the output of the first delay element is connected to the input of the record of the blocking trigger, to the second input of the fourth element OR, and the output of the second delay element to the clock input of the D-flip-flops of the output register D the inputs of the D-flip-flops of the output register are connected to the corresponding bits of the data output highway , the outputs of the D-flip-flops of the output register are connected through a group of galvanic isolation elements with a group of information outputs of the device, the output of the second delay element is connected to the third input of the fourth element that OR, the output of which is connected to the counting input of the address register, and through the first element OR, the signal conditioner, the resolution is selected, and the fifth element OR is connected by the control unit of the operating memory to the second input, the second input of the fifth element OR is connected to the command bus Manage or record data.

A positive effect in the implementation of the invention is to expand its functionality is achieved:

-strict by cell alternation of information about the premeia.points of the command and the value of the command code, the start of recording from the first cell and the sequence of recording information in the cells of RAM from the time of the appearance of the command;

-the time of the comparison element allowing the device to determine the time of issuing a command by comparing the time code stored in RAM with the current time code from the counter, which allows promptly re-arranging the start time of issuing commands and their duration before changing the code of the RAM cells;

- the introduction of the second, third, fourth and fifth OR element, the signal generator, the resolution of the sample, the third delay element, the blocking trigger and the corresponding links allows modification of the contents of the address register and the device to form other commands autonomously, to accept comparison signals only from RAM cells, in which the time base is stored, the introduction of the second delay element with the corresponding connections to record the position code information of the command code without fail in the D-triggers of the output register about clock input;

- the positioning wiring of the data output line to the corresponding inputs of the D D flip-flops of the output register allows eliminating the use of a decoder in the device;

—the use of a reference frequency generator by four to six orders of magnitude higher than the clock frequency and a frequency divider operating in standby mode increases the accuracy of issuing commands relative to the sign of starting operation.

Figure 1 presents the functional diagram of the device; figure 2 is a functional diagram of the pulse generator; Pa figs. Sa, b - algorithm for writing command codes into RAM; Fig. 4 shows timing diagrams for downloading information into the RAM.

The device contains a pulse generator 1, an address register 2, a random-access memory unit 3 (RAM), a trigger trigger A, a pulse counter 5, a comparison element b, the first 7 and second 8 group of switches, elements OR 9-13, a sampling resolution generator 14 , inverter 15, first element 1G I, first delay element 17, blocking trigger 18, second delay element 19, third delay element 20, output register 21 on D-flip-flops, group 221 ... 22m of galvanic isolation elements, highway 23 address -data, tires 24 commands otopraspeni, which include:

bus 241 - write address, bus 242 end of the exchange, bus 24z - reset, bus 2-1. | - a sign of the start of work, bus 24g - recording of data, bus 25 - execution of programs, bus 25 - clock pulses, master data 27 issuance:;, group 28 information LYHOOZ.

The pulse generator 1 (Fig. 2) is a controversial frequency generator, connected in series, element

30 And, the second divider is 31 frequencies.

The device works as follows.

There are two modes of operation: downloading information from digital computing

machines (CVM) in RAM and the formation of coded commands by the device according to the information received in RAM. The digital computer is the initiator of downloading information and transferring the device to an autonomous mode of operation.

The first mode of operation of the device.

The inputs reset the trigger 4 start, divider 31 the frequency of the counter 5. D-flip-flops output 21 register, register 2 addresses of the trigger blocking 24z- command

control signal reset. From the inverse output of the blocking trigger 18, a unit potential is applied to the second input of the first element 16 I, preparing it for operation. Zero trigger state 4

the start-up prohibits the operation of the pulse generator 1, closes the second group of switches 8, permits: writing information to the RAM and opens the first group of switches 7 through the inverter 15. The device is reset. The DVM organizes the exchange of information output (IWMD) by submitting 24 control commands, control and information words (AC and IP) on buses via address 23 data bus.

The MS (information address) is received and recorded in the ca register of address 2 at the time of arrival of the signal on the 24h bus, the address is stored and stored until the beginning of the signal by

bus 24. end of the exchange. Thus, the address of the cell is supplied to the first input of the RAM 3, and at the moment of arrival of the IC data, the fourth input / output of the RAM 3 is transmitted via the bus 24d to record the data, allowing it

(Isa) reception, OBM continues until

until all information has been written to the RAM.

The memory block has a bit greater than or equal to the counter size and corresponding to or greater than the number of output bits. For each command, the start time of the command, the position code with which the command is issued are uploaded to the RAM; command end time and zero position code. Therefore, complete information about a single command is recorded in four memory locations.

Information about each team is recorded in a strict sequence of the time of occurrence. If the beginning of several commands matches, then the position codes of these commands are added by OR and are issued by one command. When commands overlap in time in a new discrete time in which the beginning of the command is issued and there are still previous commands), the time code of the new command is issued, and the position codes of the new and existing commands are added by OR and are issued again, forming a new position code and confirming the positional command codes that still exist in this discrete time. If there are several commands in this discrete time, and one of them ends, then the time code for the command removal is issued, and the position codes of the continuing commands are added by OR and are issued again after the time code.

The position code of one command is issued by a combination of units in two bits out of 16, the remaining zeros, which allows you to receive 64 different positional commands.

This explanation of the formation of codes for loading the device RAM reads the algorithm for writing the time codes and position codes shown in FIG. B. To RAM.

After downloading the RAM block, the device is ready to issue commands in accordance with the program.

The second mode of operation of the device starts from the moment the signal is fed through bus 244, a sign of the start of operation.

The signal sign of starting the operation triggers the 4 start trigger, confirms the radial state of the blocking trigger 18, and through the fourth element 12 OR the unit — the address of the first cell of the RAM memory unit — is written through the counting input of the address register 2, through the element 10, the signal conditioner 14 starts sampling resolution.

The 4 start trigger is triggered by a single value: switches the RAM to the information output mode on the third input; the second switch group 8 opens, and the first switch group 7 closes through the inverter 15; the division of the reference frequency in generator 1 and the issuance of clock pulses relative to the sign of starting operation with an accuracy of To / K (To 0 is the period of the device's frequency of operation, K is the ratio of the reference frequency of the generator, which for automatic control devices may exceed 40,000).

5 The sampling resolution signal is fed through the third element 11 OR to the second input of block 3, and the address of the first cell to the first inputs and from the fourth input / output, the contents of the first cell of RAM 3 is output

0 to element 6, a comparison, the code from counter 5 is output to the second input of element 6 comparison.

In the absence of a comparison, the next clock pulse changes the code of the current

5 times in the counter 5, and through the second element 10 OR, the signal conditioner 14 of the resolution of the sample and the third element 11 OR from block 3 again give the code value written in the first cell. Such

0 operations will be carried out until from the comparison element 6 the value is equal to the first first element 16 I. The signal is equally fed to the first delay element 17, which holds the signal equal to a time longer than the signal resolution of the sample. The delayed signal is equally supplied: through the fourth element 12 OR to the counting input of register 2

0 addresses modify the address code;

through the fourth element 12 OR and the second element 10 OR, the signal formaker 14 of the resolution of the sample is restarted;

5 - at the input there is a record of the blocking trigger 18, which blocks the operation of the first element 16 AND;

- on the second 19 and third 20 delay elements.

0 By the signal from the signal conditioner 14, the resolution of the sample from the fourth input / output of the RAM 3 outputs the contents of the second cell and is positionally distributed to the corresponding D inputs.

5 D-flip-flops of the output register 21. To the second inputs of the D-flip-flops of the output register 21, the signal delayed by the second delay element 19 is equal and the position code of this command is recorded.

From the corresponding outputs of the D-flip-flops of the output register 21, the enabling signals are supplied to a group of galvanic isolation elements 22h-22m. Thus, at the beginning of this time interval, the code (codes) of the command (s) is set, which from the corresponding outputs of group 22i-22 of the electrical isolation elements are fed through group 28 of information outputs to the actuators.

A prerequisite for using this method of initiating an executive command is that the time of the removal of two values (2Tout) from block 3 and the clock generator error (+ At) is less than the tolerance (+ Dg) for the accuracy of issuing (removing) the command, i.e. .

/ 2ТЫЫД + Дг / .Дг ... (1)

The shorter the tolerance time of an Ag., The more stringent conditions are imposed on the speed of operation of the device and on the stability of the operation of the clock generator.

Delayed by time, exceeding Tvyd the third element. 20, the delay signal is equally applied: through the fifth element 13 OR it sets the blocking trigger 18 to the initial zero state and from its inverse output the resolving potential prepares the first element 16 for operation;

-through the fourth element 12 OR on the counting input of the register 2 addresses modify the address code;

-through the fourth element 12 OR and the second element 10 OR, the shaper of the M signal is re-enabled to allow sampling and the content of the third cell is output from the fourth input-output of RAM 3.

The formation of the command in this sample time has ended and no more operations in the device occur.

The next clock pulse changes the current time code to counters 5, and through the second element 10 OR, the signal conditioner 14, the sampling resolution, the third element 11 OR from block 3 again returns the value of the code recorded in the third cell. Such operations will be carried out until the current time code in counter 5 is equal to the time code contained in the RAM 3 cell, i.e. if a new command is issued or a previously issued one is withdrawn. The process of issuing a new command in the device will occur similarly to the above operations when issuing the first command, the process of removing a previously issued command

will be distinguished by the fact that in the even (fourth) cell of RAM 3 (where the command codes are written), there will be a zero code and, after issuing the signal, the output 21 register per

D-triggers reset. Therefore, the formation of this command is completed. The peculiarity of the operation of the pulse generator 1 is that the generation of the reference frequency generator 29 begins

0 with a power supply, and a 2 & reset signal across the busses of 24 control commands sets the frequency divider 31 to the initial zero state, and the inhibitory potential is applied to the bus 25

5 to the first input of the second element 30I. After trigger trigger A is set to one, the output of the second element 30 And the pulses of the reference oscillator appear, and the frequency divider 31 begins their division.

Claims (1)

0 Thus, the first clock pulse is measured at the output after a period of the clock frequency with an error of no more than To / K. The invention software temporary device 5 containing a pulse generator, address register, memory unit, start trigger, counter, first and second groups of switches, the first AND element, the first delay element and the output register, which is designed so that in order to expand the scope with simultaneous increasing the accuracy of issuing commands regarding the sign of operation, a comparison element, fifth elements OR, a signal generator, sampling resolution, an inverter, a lock trigger, a second and third delay elements, an output register are executed. D- triggers a pulse generator 0 is a serially connected reference frequency generator, a second And element and a frequency divider, the group of information inputs of the address register and the group of information inputs 5 switches of the first group are connected to the address-data line, the control input of the address register is connected to the control command bus. Address record, the outputs of the address register are connected to the group of information inputs of the RAM block, the group of switches of the second group is connected to the first group of inputs of the comparison element, the second group of isos which is connected with bit 5 outputs of the pulse counter, the counting input of which is connected to the output of the frequency divider of the pulse generator and to the first input of the first OR element, and the installation bypass of the pulse counter, the first inputs of the second and third elements OR, Reset Trigger Inputs, Frequency Divider and Output Register D-Triggers are connected to the Reset control command bus; input Trigger trigger record, the first input of the fourth and second input of the third element OR are connected to the control command bus Sign of start, and the trigger trigger output is connected to the first enable input of the second element And, to the control input of the main memory unit, to the second input of the second switch the group and through the inverter to the control input of the switches of the first group, the outputs of which are connected to the group of inputs and outputs of the RAM block and the group of information inputs of the switches of the second group, the second input The OR element is connected to the control command bus. The end of the exchange and its output are to the Reset register of the address, the output of the comparison element is connected to the first input of the first AND element, the output of which is through the first and second delay elements connected to the second input of the third OR element, connected to the entrance Reset trigger lock, the inverse output of which is connected to the second enable input of the second element And the output of the first delay element connected to the input records the lock trigger, to the second input of the fourth element OR, and the output of the third delay element to the clock input of the D-flip-flops of the output register. The D inputs of the D-flip-flop of the output register are connected to the corresponding data output highway, the outputs of the D-flip-flops of the output register are connected via a group of galvanic isolation elements to the group of information outputs of the device, the output of the second delay element is connected to the third input of the fourth OR element, the output of which connected to the counting input of the address register, and through the first element OR, the signal conditioner Allows the sample and the fifth element OR is connected to the second control input of the operating memory block and a second input of the fifth OR gate is connected to the bus control commands Record data. 25 Fig 1 Shig.2 U Nialo) t -.0; ABOUT h t nTo; n 0t1,2, ...; That is the duration of leriodo. THOSE8 / X NMPUYASob: Mk end positional comOnEs f K - positional command 6 of this temporary Sampling) I is the number of commands that are & uneshchh in this bucked you & Kz, s 3 ° 1is / give / e The value / ft xsdo &. 3 (END Phage 3 FIG. four