SU1753467A1 - Apparatus for representing information on screen on cathode- ray tube - Google Patents

Description

The invention relates to computing and can be used to create display devices for character and graphic information.

The purpose of the invention is to increase the speed of the device,

Fig, 1 shows a block diagram of the device; in fig. 2 - diagrams of the device.

A device for displaying information on a CRT screen contains a clock generator 1, a counter 2, a HE 3 element, a first A and a second 5 multiplexers, a decoder B, a shift register 7, a third multiplexer 8, a color memory block 9, three digital-to-analog converters 10-12, reference voltage source 13, video memory block 14, consisting of memory 15 and 16, second 17, fourth 18, third 19, fifth 20, sixth 21 and first 22 bus driver, control unit 23, first memory unit 24 commands, the first block of 25 data memories, the converter of 26 codes, the second block of command memories 27 and data memory block 28. Interface unit 29 has inputs 30,

In addition, data bus 31, control bus 32 and address bus 33 are designated.

The device works as follows.

Conventionally, the device may be Irishable consisting of three parts: the computer, the video memory and the controller.

The calculator is composed of a control block 23, a code converter 26, which are processors based on MMK Electronics MC1201 0305.019.019 TU, blocks 24 and 27 of the instruction memory, and blocks 25 and 28 of the data memory. In between, these blocks are connected by bus 33 addresses, control 32 and data 31.

The same bus blocks 23 and 26 are connected via a tire driver 22.

Image information enters via a block of 30 interfaces from a computer, a keyboard, and a mouse input device. The information processing work program is divided in half into two processors 23 and 26. Processor 26 starts processing the first image point, then sends the intermediate data to processor 23. To do this, it interrupts processor 23 via direct access (i.e., processor 23 releases address bus 33, data 31 and control 32 to access memory block 25). Recording is made through the first bus driver 22 to memory block 25. Upon completion of data recording, direct access is terminated. The processor 23 according to the received data continues to work on the calculation of the first point, and the processor 26 proceeds to the processing of the second point. From now on

Parallel operation of both processors 23 and 26 starts (Fig. 2a b). Processor 23 finishes the calculation of the first point by recording the result in the first memory 15 of video memory block 14.

Video memory is a block 14 consisting of two blocks 15 and 16, multiplexers 4, 5, and bus drivers 17-20. When the image is regenerated, the controller continuously reads information from blocks 15, 16. The address is set by counter 2. The highest bit of counter 2 is the highest address bit and indicates the switching of the first and second 5 multiplexers and bus drivers 17 and 19 (Fig. 2c, g, e). Thus, when the signal level of the high bit of the counter is low, the controller operates with block 15 through multiplexer 4 and the bus driver

17. At this time, block 16 remains free for access by processor 23 through multiplexer 5 and bus driver 20. With a high signal level of the high bit of counter 2, the controller operates in block 16

through multiplexer 5 and bus driver 19, and processor 23 proceeds to work with block 15 through multiplexer 4 and bus driver 8 Synchronization of this alternation occurs by interruption from the decoder 6 of the counter state. According to this interrupt, the processor 23 reinstalls the feature of the free video memory area and, if interpolation yields the coordinates of that video memory area, they are temporarily inserted into the drain of the memory block 25. As the required video memory is released, the processor 23 transfers data from the glass of the memory block 25 to the blocks 15 16

The controller reads the data into the shift register 7 for several points at a time and, in response to the beam movement, the CRT, by shifting, outputs codes through the multiplexer 8 to the color memory block 9. Point code goes to address

the inputs of block 8. The data corresponding to this address of block 8 are information about the color and intensity of that color for a point on the screen.

The first 10, second 11 and third 12 digital-to-analog converters convert the digital code into an analog control signal for the main color components (R, G, B). To synchronize the illumination of the signals R, G, B from the decoder 6 are issued

line and frame synchronization signals (DFI, SCI). The presence of a multiplexer 8 and a bus driver 21 allows the processor 23 to change the color palette of dots, not changing the code in blocks of video memory.

Thus, for an entire shape on the screen, shaded with the same code of dots, you can change the color and its hue with one reference to the color memory block 9.

In addition, when working with color (to change the color of a graphic figure on the screen), the increase in speed is proportional to the number of points of this figure and is measured in several orders.

Claims (1)

An apparatus for displaying information on a cathode-ray tube (CRT) screen containing a clock generator, the first output of which is connected to the input of a binary counter-frequency divider, a decoder, the first and second outputs of which are outputs of the device synchronization signals, shift register, first a multiplexer, the outputs of which are connected to the first address input of the video memory unit, the address inputs of the first multiplexer are connected to the device address bus, the control unit, the first blocks. program memories and data, the first bus driver, the first, second and third outputs of which are connected respectively to the data buses, controls and addresses, the source of the reference voltage, connected to the control inputs of the first and second digital-analog converters, whose outputs are first and second The second information output of the device, characterized in that, in order to increase the speed of the device, it contains a code converter, second blocks of program and data memory, the second and third multiplex xors, color storage unit, second to sixth bus drivers, third digital-to-analog converter, the control input of which is connected to the voltage source, and the element NOT, the inputs of the first bus driver, respectively, connected to the data buses, control and address which are connected respectively to the inputs-outputs of the code converter and the second program memory blocks and data, the interrupt input of the code converter is connected to the output of the control unit, the interrupt input of which is connected to the third output of the decoder, the fourth the output of which is connected to the control input of the register of the shift, the input of the control of the shift of which is connected to the second output of the clock generator, the inputs of the decoder are connected to the outputs of the binary counter-frequency divider connected to the information inputs of the first and second multiplexers, the address inputs of the second multiplexer are connected to the address bus, to which the address inputs of the third multiplexer are connected, the control input of which is connected to the control bus, and the information inputs to the outputs of the shift register, output s second multiplexer connected to the second address the input of the video memory unit, the outputs of the third multiplexer are connected to the address input of the color storage unit, the control input of which is connected to the Control Bus, and the inputs / outputs are connected to the information inputs of the first, second and third digital-analog converters and the outputs of the sixth bus driver, the input control unit is connected to the control bus, and information inputs - to the bus the data outputs to which the fourth and fifth bus drivers are connected, the information inputs of the second and fourth bus drivers are connected to the first output of the video memory block, the second output of which is connected to the information inputs of the third and fifth bus drivers, the control inputs of the first and second multiplexers are connected to the output of the higher bit binary counter-divider part, connected to the control input of the second bus driver and input 1 of the element NOT, the output of which is connected to the control input of the third bus driver, output The third digital-to-analog converter is the third information output of the device. H) 4J - -y - -7 .IIMI lsch e " el  tuiiiii - QUIET I  Iiiiiiii | School - shp 3; Iimiiil n -Vu E Shish v C 31 ( 4 (1 II N 3 fr t W. $ s  i  $ L X. chg § L 1 B «§5 about tH   i 7 dl-. |