JPS6145839B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an attribute control device for controlling the appearance of displayed characters in a raster scan type display.

First, a conventional CRT display will be explained with reference to FIG. In the figure, numeral 100 is a timing control circuit that generates all timing signals necessary for a CRT display. Its basic constituent blocks are shown in FIG. 2, and its time chart is shown in FIG. 3.

In FIG. 2, reference numeral 110 is a reference clock generator, the output of which is used for a dot counter 120 that determines the number of horizontal dots in one character, a character counter 130 that determines the number of horizontal characters in one line, and a raster counter that determines the number of vertical dots in one character. 150, and a line counter 160 that determines the number of vertical characters in one frame sequentially counts down to generate the necessary timing. That is, the output 115 of the reference clock generator is a clock pulse in units of character dots and is used to serialize the output of the character generator, and the output 125 of the dot counter 120 is a clock pulse in units of character dots.
A character-based clock signal used for attribute control circuits and other purposes. Output 135 of horizontal character counter 130 and vertical character counter 1
The output 165 of the decoders 140 and 170 is used as an address signal for reading character data from the refresh memory, and the outputs of the decoders 140 and 170 are used as horizontal synchronizing signals and vertical synchronizing signals for controlling the beam deflection of the CRT display. Also, raster counter 1
The output 155 of 50 is used as the raster select signal for the character generator.

Now, returning to Figure 1, 200 is the processor,
300 is the program memory, 400 is a refresh memory that stores one frame of display data, and its contents are stored in the address bus of the processor 200.
Can be rewritten by AB and data bus DB specifications. On the other hand, display data is read out from the refresh memory by the output 135 of the horizontal character counter and the output 165 of the vertical character counter, and the character code 410 is output to the character generator 500. In addition to the character code, the output 155 of the raster counter is input to the character generator 500.
Parallel dot pattern 51 of specified raster of specified character
Outputs 0. This output is converted into a serial dot pattern 610 by a parallel to serial converter 600 at the clock rate of the dot clock signal 115, and is input to an attribute control circuit 700. In addition to the above, a timing signal 125 and an attribute control signal 420 from the refresh memory 400 are input to the attribute control circuit, and color control and blinking control of displayed characters are performed here. Characters are displayed on display 800.

The attribute control circuit 700 will now be explained. The attribute control circuit executes control related to display modes such as display color control and blinking display control. There are two types of attribute control: character attribute control that allows you to change the display mode for each character, and field attribute control that allows you to change the display mode for each field that includes multiple characters. The attribute control signal is sent to the refresh memory 400.
This is reflected in the display data read from.

FIG. 4A shows an example of the structure of display data in the case of character attributes.

In the figure, the display data consists of 11 bits, and character codes are given to bits 0 to 6.
An attribute related to blinking and three attributes related to color are given to 7 to 10 bits. That is, in the case of a character attribute, an attribute for controlling the display mode is given for each display character, so it is possible to control the display color and blinking on a character-by-character basis.

FIGS. 4B and 4C show an example of the structure of display data in the case of a field attribute. In the case of a field attribute, the display data has two data configurations: one indicating a character code and one indicating an attribute control signal.

In FIG. 4B, the display data consists of 8 bits, and when the 7th bit is "0", the 0th to 6th bits are processed as a character code.

Next, in FIG. 4C, the seventh bit is "1", and in this case, the display data indicates an attribute control code, each of bits 0 to 6 is processed as an attribute control signal, and these attribute control signals is controlled to remain unchanged within one field, that is, until the next attribute control code is read. Therefore, in the case of field attributes, the display color and blinking of characters can be controlled in units of fields consisting of a plurality of characters.

Each of the above two types of attribute control has its advantages and disadvantages. That is, while character attribute control has the advantage of being able to change the display mode on a character by character basis, it has the disadvantage that the bit length of display data becomes large and the refresh memory becomes large. On the other hand, field attribute control has an inferior display function because the display mode can only be changed in field units, but has the advantage that the refresh memory can be made smaller because the bit length of the display data is small.

In conventional displays, which attribute control method to use is fixed for each model. Therefore, in order to meet the diverse needs of users, it is necessary to manufacture at least two independent models, which has the drawback of doubling the various costs and resulting in an expensive device. Further, some users may request the combination of character attribute and field attribute in the same model, but it has not been possible to respond to such requests at all.

SUMMARY OF THE INVENTION An object of the present invention is to provide a new attribute control device that eliminates the above-mentioned drawbacks.

The gist of the present invention is that it is configured to enable both character attribute control and field attribute control, and that character attribute control can be performed in units of individual attribute control signals using program specified registers or switches. , it is possible to specify field attribute control, thereby making it possible to realize a new display system in which both types of attribute control coexist.

Details of the invention will become apparent from the following description and drawings.

FIG. 5 shows an embodiment of the invention. In the figure, reference numeral 10 denotes a mode changeover switch, which allows selection of either character attribute or field attribute. First, the operation when the switch 10 is on is a character attribute, and when the switch 10 is off is a field attribute. In this case, since the output of the NAND gate 63 is always at a high level, the outputs Y ₀ to Y ₃ of the multiplexer 20 are connected to the refresh memory 4.
Attribute signal 420 from 00 is selected and provided to attribute register 30.
The set signal to the T terminal of the attribute register 30 is the refresh memory output timing valid for display because the output of the NAND gate 61 is always at a high level.
is supplied from the output of the NAND gate 62. Therefore, the attribute register 30
is the attribute signal 4 in units of 1 character time.
20 states are sampled and output. Among the outputs of the attribute register 30, the color control signals Q ₁ , Q ₂ , Q ₃ are sent to the three-input AND gate 52,
53 and 54, and a blinking control signal Q ₀ is applied to the first input of the NAND gate 51. And the second of Nand Gate 51
The blinking period signal BLKTMG from the timing control circuit is applied to the input of the gate, and the output thereof is connected to the second input terminal of the AND gates 52, 53, and 54. A serial video signal (PSOUT) 610 from a parallel-to-serial converter 600 is applied to third inputs of the AND gates 52, 53, and 54. Therefore, this results in AND gates 52, 53, 54
Video signals RV, GV, and BV are output from which the color and blink are controlled on a character-by-character basis.

Next, a case will be described in which the switch 10 is turned off and the feed attribute is set. In this case, the multiplexer 20 selects and outputs the attribute control signal 420 when the attribute designation bit F shown in FIG.
When is the start of a row when not HSTRT?
HSTRT and attribute specification bit F
When is “0”, previous row attribute register 4
An output of 0 is selected and output. The input of the previous row attribute register 40 is connected to the output of the attribute register 30, and when the raster clock (RSCP) 136 is "1", the final timing of the row is reached.
Set with the inverted signal of character clock (CHCP) 125 at HEND. As shown in the field attribute display example in Figure 7, this means that the attribute specified by field code _F2 is
This is to ensure that it is maintained until just before field code _F3 on the next line. In addition, Fig. 6 shows the fifth
MOTMG, HSTRT, HEND used in figure explanation
A time chart showing the timing relationship is shown.

In addition, Fig. 8 shows the attribute control signals (R, G, B) for character attributes.
A time chart showing the relationship between the color video signals (RV, GV, and BV) is shown. In the illustrated example, for convenience, the color of the characters is changed in units of two characters. Furthermore, Fig. 9 shows attribute control signals (R, G, B) and color video signals (RV,
A time chart showing the relationship between GV and BV is shown.

Next, another embodiment of the present invention will be explained with reference to FIG. In the figure, the configurations of the multiplexer 20, attribute register 30, and preceding attribute register 40 are the same as in the embodiment shown in FIG.
The select signal of multiplexer 20 and the set signal of attribute register 30 are different. That is, in this embodiment, the above-mentioned components operate only for attribute control in field units. Therefore, the multiplexer 20 selects the attribute control signal 420 only when the output of the refresh memory indicates an attribute control character (F=1) and when it is not at the first display position of the line.
In other cases, the previous row attribute register 40
The selected output is output to the field attribute register 30. In addition, the field attribute register 30 is the first display position of the line.
HSTRT and the attribute control character (F=
A set signal is applied only in case 1). Therefore, the outputs Q ₁ to _{Q 3} of the field attribute register 30 hold attribute control signals for each field.

Next, register 70 is a character attribute register for setting attribute control signal 420 character by character, and its outputs Q ₀ -Q ₃ are connected to one input of multiplexers 81 - 84. The outputs Q ₀ -Q ₃ of the field attribute register 30 are connected to the other input terminals of the multiplexers 81 - 84 . The outputs _Q0 to _Q3 of the attribute specification register 90 are connected to the select terminals S of the multiplexers 81 to 84, and depending on the contents, the character attribute or the field attribute is selected for each attribute control signal. One of the views is selected and output to the video control circuit 65. Inputs D ₀ to _{D 3} of the attribute designation register 90 are connected to data buses DB ₀ to _{DB 4} of the processor 200, and their contents can be freely set using a write signal WR.

Furthermore, in a system that does not include a processor, a switch shown in FIG. 12 can be used in place of the attribute assignment register 90 to select either a character attribute or a field attribute.

Note that FIG. 11 shows an example of the data structure of the refresh memory when character attributes and field attributes are used together.

In FIG. 11A, the 7th bit is F=0, and in this case, bits 0 to 6 indicate a character code, and bits 8 to 10 indicate a character attribute control signal.
In addition, in FIG. 11B, F=1, and at this time,
Bits 0 to 6 indicate field attribute control signals. Therefore, in this example, three character attributes and seven field attributes can be controlled with an 11-bit data configuration.

As is clear from the above explanation, according to the present invention, one attribute control circuit can selectively use either character attribute beat control or field attribute control, and each attribute can also be controlled individually. This is because the control method can be selected between character attribute and field attribute. A single attribute control circuit can meet the diverse needs of users, contributing to cost reduction and functional enhancement of display systems.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional CRT display, Figure 2 is a block diagram of a timing control circuit, Figure 3 is a time chart of a timing control circuit, Figure 4 is a data diagram of a refresh memory, and Figure 5 is a diagram of a data configuration of a refresh memory. The figure shows an embodiment of the attribute control circuit according to the present invention, FIG. 6 shows a time chart of various timing signals, FIG. 7 shows an example display for field attribute control, and FIG. 8 shows a character attribute control circuit. FIG. 9 is a time chart of the attribute control signal and color video signal of the field attribute, FIG. 10 is another embodiment of the matrix control circuit according to the present invention. 11 is a data configuration diagram of a refresh memory in which character attributes and field attributes coexist, and FIG. 12 is a configuration diagram of a changeover switch for attribute master sign. 400... Refresh memory, 700... Attribute control circuit, 800... CRT display, 10... Switch, 20... Multiplexer, 30... Attribute register, 40...
Previous row attribute register.

Claims (1)

[Claims] 1. In a display attribute control device that is provided between a raster scanning display and a refresh memory and performs attribute control for display mode control, it is possible to specify switching between a character attribute and a field attribute. a multiplexer for switching and outputting either the first attribute control signal from the refresh memory or the second attribute control signal corresponding to the last displayed character of the previous line according to the specification of the switching specifying means; An attribute register that holds the first or second attribute control signal, which is the output of the multiplexer, in character time units, and an attribute register that holds the output of the attribute register at the timing of the last character of the display line, and stores the held contents as described above. A preceding attribute register is provided to be input as the second attribute control signal of the multiplexer, and when a character attribute is specified by the switching specifying means, the output of the multiplexer is input as the first attribute control signal. When performing attribute control for each switching character and specifying a field attribute using the switching specification means, only when the output of the refresh memory is the specified character and is not the first display character of the line, Attribute control of a display characterized in that the output of the multiplexer is switched to a first attribute control signal, and at other times, the output of the multiplexer is switched to a second attribute control signal to perform attribute control for each field. Device.