SU1737511A1 - Magnetic bubble domain storage - Google Patents

Abstract

The invention relates to computing and can be used in the construction of devices for storing discrete information on cylindrical magnetic domains (CMD). The purpose of the invention is to simplify the device and increase its speed. The goal is achieved by introducing one VN (1 + logan) memory block instead of two RAMs, an OR element, a two-bit counter, which makes it possible to remember the addresses of bits containing errors in information blocks and a sign of a corrected error, to start the information recovery mode in the controller stored in the drive on the CMD, with an error count of up to K, 4 Il.

Description

with

WITH

The invention relates to computing and can be used in the construction of storage devices for discrete information on cylindrical magnetic domains (CMD).

A memory on a CMD is known that contains an information accumulator on a CMD, a controller, a recording unit, a readout unit, an error detection and correction unit, an error counter, and a random-access memory block (RAM) with a capacity of 2xN bits (where N is the number of information blocks in the accumulator on CMD), which stores the addresses of information blocks in which errors are detected.

This device performs the correction of single errors and the detection of double errors in the CMD-drive, and when a certain amount of errors are accumulated to - the recovery of information in the drive. However, this device lacks the possibility of correcting double faults, the occurrence of which can lead to a failure of the device as a whole.

The closest known device to the proposed is a memory device on the UMD containing a controller, an element of addition modulo two, an error detection and correction unit, an information storage unit, an information reading unit, an OR error counter element, the first NVR unit with a capacity of VN -2, in which signs are correctable error (KO) and uncorrectable error (NKO), the second block of the RAM with the capacity VN (log2n) (where n is the length of the information block), in which the address of the error bit in the information block, two AND elements and the comparator are written.

This device has the ability to correct m + 1 multiple errors (double errors with m 1), using

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a correction code correcting m multiple / single with m 1 / and detecting m + 1 multiple errors (double with m 1) by storing the addresses of the bits containing errors in the information blocks.

However, the correction of double errors in this device is achieved due to the considerable complexity of the device and the algorithm of its operation.

The purpose of the invention is to simplify the device and increase its speed.

This goal is achieved by the fact that a device containing an information storage device whose input and output are connected respectively to an output of an information recording unit and an input of an information reading unit, a controller whose input-output group is a device input-output group, an error correction and correction unit, the first input of which is connected to the first input of the controller, and the first output is connected to the input of the information recording unit and the data input of the controller, the error counter, the output of which is connected to the group of inputs of the signal device The controller’s controller, a comparator, the second inputs of which are connected to the third outputs of the error detection and correction unit (BKO), the first AND element, the first input of which is connected to the output of the CO BRR, the addition element modulo two, the second element AND, characterized in that in order to simplify the device and increase its speed, it contains a block of RAM, the address inputs of which are connected to the second inputs of the controller, information inputs are connected to the third inputs and output, the GER error is corrected, information outputs on are connected to the first group of inputs of the comparator and the first input of the first element OR, the output of the first element OR is connected to the counting input of the error counter and the control input of the main memory unit, the output of the comparator is connected to the first input of the modulo-two element, the second input of which is connected to the output reading unit, and the output is connected to the first input of the second OR element, the second input of which is connected to the third output of the controller, and its output is connected to the second input of the ACU, the second input of the first element I is connected to the input ementa modulo two BKO, a second AND gate having a first input connected to the output of the corrected error BKO, of the two-bit counter, the count input of which is connected to the output of the first element

And, the input of the set to zero of which is connected to the output of the second element I, the direct output of the first bit of which is connected to the group of conditional signals of the controller, the inverse output of the second bit connected to the second input of the element AND, the second input of the first element OR and the group of signals of the conditional controller .

The newly introduced elements, a RAM block with a capacity of V N (1 + Iog2n) instead of two RAMs, an OR element, a two-bit counter, make it possible to remember the addresses of bits containing errors in information blocks and the TO attribute to start

in the controller, the recovery mode of information stored in the drive on the CMD when the error counter counts to K.

Thus, the proposed device exhibits a new property - the simplification

devices and reducing the double error correction time by entering one RAM block instead of two RAMs, storing the address of the corrected error and its sign (FD), which, unlike the well-known devices, prevent the writing of the second bit address containing the error to the RAM in the information block at its occurrence, which is corrected in the cash register,

thus, there is no need to re-read the information block and determine the type of error (failure or permanent error), which was carried out in a known device, in the proposed device instead of two RAMs (with capacities V N-2 and VN (log2n), one RAM is used Fig. 1 is a block diagram of the proposed device; Fig. 2 is a block diagram of the controller; Fig. 3 and 4 shows an algorithm for the operation of the device.

The device comprises (Fig. 1) a controller 1, an element 2 of addition modulo two, a block 3 for detecting and correcting errors,

including the node 4 for the detection and correction of errors, the block 5 of the buffer memory, the counter 6 of the address, the element 7 addition modulo two, the block 8 of recording information, the drive 9 of information on the CMD, block 10 of reading

information, the element OR 11, the counter 12 errors, the block 13 of the RAM, the element OR 14, the elements AND 15 and 16, the counter 17, the outputs 18 of the controller 1, the comparator 19, the group 20 of the inputs of the signals of the conditions of the controller 1, the input 21 of the controller, outputs 22 and 23 of controller 1. Controller 1 contains (FIG. 2) register 24 of the initial firmware address, driver of the microcommand address 25, microgramgram memory block 26, microcoad register 27, microprocessor 28, condition code multiplexer 9, register 30, register 1 read, buffer register 32, register of the current address, desh Rathore 34 base Dres.

The device works as follows.

In the write mode, when accessing the device, the decoder of the base address 34 allows the command code written from the system to be written into the initial address register of the microprogram 24. This code is converted by the microcommand address formation circuit 25. The microinstruction stored in the firmware memory block (IHD) 26 is the corresponding address is fed to the micro-command register 27, the bits of which are used to control the operation unit and the firmware control unit. Under the microprogram control, the information block is received from the system bus via the write register 30 to the microprocessor 28. Then, via the third output 22 of the controller 1, it is transmitted to the error detection and correction block 3, where the check bits are formed. After this, the information block is recorded by means of the recording block 8 into the drive on the CMD 9.

In the read mode, the information unit under control of the microprogram is read on the drive on the CMD 9 and is fed through the readout unit 10 to the error detection and correction unit 3, then via the internal bus 21 via the buffer register 32 to the microprocessor and then through the read register 31 to the system bus.

If an error is detected in the information block, the flag of an error-correctable error (NCB) or an error-correctable error (CR) appears at the corresponding output of the error detection and correction block 3.

An error is considered unstable, to correct which a repeated read operation is sufficient. A stable error is considered such an error, for which correction information is necessary to correct.

In the proposed device, two independent errors in the information block are correctable, and uncorrected errors are three and more errors.

In the read mode, the information block is read from the drive on the CMD 9 and is fed through the information read block 10 to the block 3 for the detection and correction of errors. If BKO 3 detects an uncorrectable error (NCB 1), then the controller issues an uncorrectable error message to the system and can continue to work. J

if BKO 3 does not detect an error

(QO 0), then the next information block is sampled.

If BKO 3 detects a correctable error (KO 1), controller 1 analyzes the FO signals from the output of block 13 and KO with

0 direct output Q of counter 17 arriving at input 20 of the multiplexer of condition code 29 of controller 1. If KO 1, and in RAM 13 at this address the flag FD 1 is written, i.e. the second error is detected then in contrast

5 is not required from the known re-reading device of the information block at this address, since the first error is corrected at the input of the GER 3 at the address of the error bit from block 13, and the second is corrected in the GER 3.

If the ACU 3 sets the feature KO 1, and in the RAM 13 at this address the FD 0 is written, the counter value is incremented, and the information block is re-read.

If during repeated reading the block 3 of detection and error correction (BS) sets the flag KO 0, then the information block was unstable

0 the error and the correction operation of the information on the current address is not required, the next information block is sampled. When you re-detect the error (KO 1) from the output of the logical element OR

5 11 the write enable signal goes to the input of the highlight 13 of the sign F0 1, the error bit addresses, the contents of the error counter is increased by one and the error in the BKO 3 is corrected. In the initial state of the block 13 all zeroes, the addresses of the error bits from one and further, the contents of the error counter and the counter are zero. At the current address of the information unit, which is fed to the input of the RAM 13

5 from the register output of the current address 33 of the controller 1, the block 13 records the address of the error bit in this information block, the bit flag of the error bit FO, and the contents of the error counter 12 are increased by

0 unit. On subsequent calls to this information block, the address of the error bit from block 13 is input to the comparator 19, the second input is the address of the bit from the output of the counter of the address of the RAM 6,

5 if the addresses match, the comparator 19 outputs a signal to the input of element 2 modulo two sum, to the second input of which information bits are received. The signal from the output of the comparator 19 inverts the error bit, the address of which is recorded in block 13,

and the second error is corrected by the correction code of the BSO 3. Controller 1 analyzes the recovery flag of the PV information received on the multiplexer of the condition code 29 from the output of the error counter 12. If the FS 1, overwrites the information at the addresses of the information blocks in which errors occurred with the algorithm shown in FIG. If the PV is 0, the controller 1 operates in the read or write mode, by analyzing the NPO flag from the output of the cash register and the DC from the direct output Qi of the counter 17 and, if necessary, the information is corrected in accordance with the algorithm shown in Fig. 4. When the number of information blocks in which errors are detected reaches K, i.e. the contents of the error counter 12 is K, the output of the overflow error counter appears 1, which is a sign of the PV and the controller starts operation in the recovery mode according to the algorithm in FIG. The symptom of PV 1 may also be set by a timer interrupt signal.

In the error correction mode, when the FW 1 flag is set, a read signal is sent to the control input of the block, and the address input is supplied from the register of the current address 33 of the controller 1. At this address, the error flag bit (FO) is read from the RAM 13, and if the FD is 0, then the address counter of the information block is incremented by one until the addresses of all the information blocks are viewed. If FD 1, the information block at this address is read and the first error is corrected at the input of the BKO 3 in accordance with the address of the error bit from block 13, and the second error, if any, is corrected in the BKO 3 and the contents of the error counter are decremented. After the errors in the information block are recovered, the information block is written to the drive on the CMD 7 at the address from the register of the current address 33 of controller 1. After the addresses of the error bits of all the information blocks that generated errors are retrieved from the RAM 13, the contents of the error counter 12 zeroes out and outputs the signal FV 0 to the input of the multiplexer of condition code 29 of controller 1.

Upon receipt of the PV 0 signal, the controller 1 starts the work on the microprogram, the algorithm of which is presented in FIG.

Claims (1)

A memory device on cylindrical magnetic domains containing an information storage device whose input and output are connected respectively to an output of an information recording unit and an input of an information reading unit, a controller whose input-output groups of which are input-output groups of a device, a block error detection and correction, the first input of which is connected to the first output of the controller, and the first output is connected to the input of the information recording unit and to the data input of the controller, the error counter, the output of which is connected to the inputs of the conditional signals of the controller group, the counting input of the error counter is connected to the output of the first element OR, comparator, the inputs of the second group of which are connected to the outputs the group of the error detection and correction unit, the first element is AND, the first input of which is connected to the output. The error of the error detection and correction unit is corrected, the addition element modulo Two, and the second element, characterized in that, in order to simplify the device and increase its speed, a memory block is inserted into it, the address input of which is connected to the second output controller, information inputs - with group outputs and output Error correction and error correction block are corrected, information outputs - with inputs of the first comparator group, first input of the first OR element, and with inputs of the controller group condition signals that control the input-output of the first OR element, the output of the comparator is connected to the first input of the addition element modulo two, the second input of which is connected to the output of the information reading unit, and the output to the first input of the second OR element, the second input of which is connected with the third output of the controller, the output of the second OR element - with the second output of the error detection and correction unit, the second output of which is connected to the second input of the first element AND, the second element AND whose first input is connected to the output Correctable error detection and correction unit, counter, the counting input of which is connected to the output of the first element And, the installation input of the counter is connected to the output of the second element And, the second the input of which is connected to the inverse output of the counter and the second input of the first element OR, the direct output of the counter to the inputs of the conditions signals of the controller group. to / from sisgem.shany FIG. one Reading bit DOF from ZU L V Restore Suma owuSxu In Cmp on current. address Fig.Z Reading iio block of CMD pam clay Correction error at the entrance of the 6th to the address from the memory unit l in Record (P0- / los „at the address of the NVR Correction error 8 ff / CO