SU1721833A1 - Channel selector - Google Patents

Abstract

The invention relates to radio engineering and can be used in multichannel pulse signal processing systems for sampling a channel within a predetermined frequency range. The aim of the invention is to enhance the functionality by controlling interference such as pulse drop. The device contains shapers 1.11, triggers 2.12, elements And 3,4,13. the OR element, the counters 6, 10, 14, and 16, the pulse generator 7, the frequency divider 8, the switch 9, and the memory block 15. If during one period of the input signal the counter 10 does not overflow, then the device is in the specified channel. Otherwise, when the counter 14 overflows, the counter 6 changes the frequency of the pulses coming through the switch 9. 1 sludge.

Description

The invention relates to radio engineering and can be used in multichannel systems for processing pulse signals to select a channel within a given frequency range.

A device is known in which automatic selection of a frequency channel is carried out using a scaling unit, a band overload fixation unit, a decoder, a start unit, a delay unit, and a storage unit.

The disadvantage of this device is that in the presence of interference, primarily interference such as loss of pulses, it is difficult to correctly scale the input signal in the scaling unit, which means that it is possible to erroneously determine another channel.

The closest in technical essence to the invention is a device for selecting a channel, containing a serially connected oscillator, a counter and a first memory block, as well as a switch, a comparison circuit and a second memory block, codes corresponding to the input signals of various channels, a control input are supplied to the information inputs of the switch the switch is connected to the output of the counter, the output of the switch is connected to the inputs of the comparison circuit and the second memory block, the second input of the comparison circuit is connected to the output of the second block RAM memory, and an output - to the control inputs of the first and second memory blocks. The channel number is generated by the oscillator and the counter and is recorded in the first memory block by the enable signal from the comparison circuit if, for a given channel number, a code corresponding to that channel is present on the information input of the switch.

A disadvantage of the known device is that it does not send the signals themselves to the inputs of the switch, but codes characterizing the signals, since using it as a device to select the frequency channel to which this real signal belongs cannot be received directly from the received signal without additional equipment .

The purpose of the invention is the expansion of functionality.

This goal is achieved by the fact that in the device for selecting a channel containing a pulse generator, a switch, a memory unit and a first counter, the outputs of which are connected to the inputs of the memory unit and with the control inputs of the switch, series-connected second and third counters, series-connected first shaper, the first trigger, the first element And, the first input of which is combined with the first input of the second element And, the third element And, a frequency divider connected between the output of the pulse generator and the information the inputs of the switch, the fourth counter, the output of which is connected to the control input of the memory unit, the second driver, connected in series with the input of the first driver and is the input of the device, and the second trigger, the output of which is connected to the second input of the third element AND, the OR element, output which is connected to the reset input of the second counter, the output of which is connected to the reset input of the second trigger, and the counting input with the output of the second element And, the second input of which is connected to the output of the switch and the output of the third element And is connected to the counting input of the fourth counter ,. the reset input of the third counter and the first input of the OR element, the second input of which is combined with the counting input of the first counter and the output of the third counter, and the output of the first driver is connected to the second input of the first element I.

The drawing shows a diagram of a device for selecting channels.

The device comprises a first driver 1, a first trigger 2, a first AND 3 circuit, a second And 4 circuit, a first OR 5 circuit, a first counter 6, a generator 7, a frequency divider 8, a switch 9, a second counter 10, a second driver 11, a second trigger 12 , the third circuit And 13, the third counter 14, the memory unit 15 and the fourth counter 16.

Circuits AND 3,4 and 13 are standard two-input circuits AND, circuit OR 5 - standard two-input circuit OR. As triggers 2 and 12, RS triggers can be used. Shaper 1 generates a short pulse along the rising edge of the input pulse signal or when the input harmonic signal crosses the zero level with a positive derivative, and the second shaper 11 generates a short pulse along the falling edge of the input pulse or when the input harmonic crosses the zero level with the negative derivative. In the case of pulsed signals, the shapers 1 and 11 are constructed according to schemes known in digital electronics using inverters, I-NOT circuits, or multivibrators of the K155AP and K155AGZ type, and in the case of harmonic signals 1721833, the fishes are constructed according to known schemes using comparators.

As the generator 7, you can use any stable circuit, a high-frequency pulse generator. A frequency divider 8 divides the frequency of the oscillator 7- and has η outputs, is constructed as a counter-divider according to known schemes from series-connected integrated counters, od <

The switch 9 according to the code supplied to its control inputs, connects the corresponding input to its output, passing pulses of a given frequency to the output. The switch 9 is built according to known schemes using integrated comparator-multiplexers.

In block 15 of the memory codes are stored corresponding to the channel numbers. This actually buffer memory can be implemented I on the register using integral D-triggers or integral registers.

Counters 6,10,14 and 16 are binary counters having a counting input and a zero output. Counters 10.14 and 16 should also have an overflow output. All counters are easily implemented using integral counters of the K155IE7 type (for counter 6, you can also take K155IE5).

The device operates as follows.

Initially, all the triggers and counters are reset (zeroing circuits are not shown), and the zero code of the first counter 6, arriving at the switch 9, allows passage through the last clock pulse from the frequency divider 8 of the highest frequency.

Along the front of the first output pulse, the first trigger 2 is set to unity, allowing the passage of clock pulses to the second counter 10 from the switch

9. The length of the second counter 10 and the frequency of the clock pulses at the output of the frequency divider 8 are selected so that for the input signals of this channel (the channel number code is determined by the contents of the first counter 6), overflow of the second counter 10 would occur only when the pulse disappears (due to interference or the proper form modulation). If there is no overflow of the second counter 10, then the second trigger 12 is set to a single state along the falling edge of the input pulse, allowing the pulse from the first driver 1 corresponding to the leading edge of the second input pulse to go through the IZ and 13 circuits and write to the fourth counter 16. and also reset the second 10 and third 14 counters. . ; ''

If the second counter 10 works almost without overflows (overflows are rare and are associated with interferences such as pulse loss), then after the fourth counter is 16 (* s3c4) 0 ^^. ((Speriodo0? Input signal without overflow (t < 8), according to the signal from the four ^ counter? Counter 16, the code from the first counter 8, corresponding to the channel number code, is written to the memory unit 15. If the second counter 10 is constantly full (the trigger 12 is reset to zero, locking the AND 13 circuit and prohibiting counter 16 to count periods with overflow), the number of overflows counts the third count chik 14. If this number exceeds K, where K is the largest possible number of consecutive pulses missing, then the overflow signal from the output of the third counter 14 resets the second counter 10 and adds one to the first counter 6, i.e., the check for the input signals to the next The overflow pulse of counter 16 can serve as a signal for ending the selection of the channel number, and the channel number code is removed from the memory unit 15.

Experimental studies of the model of the proposed device for selecting a channel completely confirmed its operability using real modulated pulse signals.

Thus, the introduction into the circuit of the device for selecting a channel with the corresponding connections of three counters, two triggers, two formers, three AND circuits, an OR circuit and a frequency divider allows you to use the device to estimate the channel number directly from real input signals subjected to modulation and distorted noise, what can be considered an extension of the functionality of the device. This has a positive effect.

Claims (1)

Claim A device for selecting a channel containing a pulse generator, a switch, a memory unit and a first counter, the outputs of which are connected to the inputs of the memory unit and to the control inputs of the switch, characterized in that, in order to expand the functionality by controlling interference such as pulse loss, it is introduced the second and third counters connected in series, the first shaper connected in series, the first trigger, the first element And, the first input of which is combined ό the first input of the second element And, the third element nt And, the frequency divider connected between the output of the pulse generator and the information inputs of the switch, the fourth counter, the output of which is connected to the control input of the memory unit, the second driver is connected in series, the input of which is combined with the input of the first driver and is the input of the device, and the second trigger, the output which is connected to the second input of the third AND element, the OR element, the output of which is connected to the reset input of the second counter, the output of which is connected to the reset input of the second trigger, and the first input is the output of the second AND element, the second input of which is connected to the output of the switch, and the output of the third AND element is connected to the counting input of the fourth counter, the reset input of the third counter and the first input of the OR element, the second input of which is combined with the counting input of the first counter and the output the third counter, and the output of the first driver is connected to the second input of the first element I.