SU1711213A1 - Entire status annunciator - Google Patents

Abstract

The invention relates to signaling and can be used to control a large number of objects. The aim of the invention is to increase the information content of the device. The purpose of the invention is achieved by the fact that the device containing information input 1, memory block 2, counter 5, first element I 7, start block 8, element OR or NOT, display block 11 information, switch 12, generator 14 impulses and control input 16, cyclic code generator 3, element OR 4 is entered. trigger 6, second element 9, delay element 13, pulse generator 15. The device allows you to control a large number of objects in many ways. With healthy objects, the survey of the latter is carried out with great speed. In the event of malfunctioning, the survey is conducted with a low frequency and a long illumination of the numbers of the faulty object and j of its anomalous parameters. 2 or;

Description

Phie.1

This invention relates to signaling and can be used to monitor the state of a large number of objects.

The aim of the invention is to increase the information content of the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 - functional diagram of the cyclic code generator.

The device contains information input 1 of the device, memory block 2, cyclic code generator 3, element OR 4, counter 5, trigger 6, element 7, start block 8, element 9, element OR NOT 10, information display block 1.1, a switch 12, a delay element 13, a pulse generator 14, a pulse shaper 15, a device control input 16 and a device address input 17.

Cyclic code feed 3 may be made in the form of serially connected controllable distributor 18 pulses and encoder 19. The control inputs of the controllable pulse distributor 18 are information inputs of the cyclic code generator 3, and its clock input is the clock input of the cyclic code generator 3.

The installation input and the output of the end of the cycle of the controlled distributor 18 pulses are respectively the input of the installation and the output of the end of the cycle of the generator 3 of the cyclic code. The output of the encoder 19 is the output of the cyclic code generator 3.

The start-up unit 8 can be made in the form of a single pulse shaper triggered by a button included in the unit, and a signal from the output of the And 7 element.

As a display unit 11, a digital display can be used.

The pulse shaper 15 may be configured as a single pulse shaper with a duration sufficient to perform the monitoring cycle.

The device works as follows.

When a pulse is formed by the start-up unit 8 (when the button is pressed), O is recorded in all the cells of the memory block 2. The pulse shaper 15 is triggered by the same signal. At the output of the latter, a signal 1 is generated for the time of receiving information into memory block 2 by information input 1 in accordance with the address at the device 17 address input, passed in this case by the switch 12. Address and information are synchronized by external means. In this case, either the absence of an address with a code 0 ... 0 at address input 17, or the absence of a signal 1 at information input 1 with an address with a code 0 ... 0 must be provided.

For each address I, information pulses (if present) from information input 1 set the corresponding J-th trigger of column I of memory block 2 to state T. Thus, each address I corresponds to column i of cells of memory block 2. In this case, the signal 1 from the output is formed. pulse pulse 15 turns off the information display unit 11. His scoreboard is not there, which indicates the reception of information in memory block 2. With the same signal, counter 5, trigger b, cyclic code generator 3 are set to state O and generator 14 is inhibited.

0 pulses.

At the end of the cycle of receiving information at the output of the pulse former 15, an O signal appears, including an information display unit 11 and enabling

5 generator 14 pulses. At the same time, in one discharge, the display of the information display unit 11 sequentially highlights the numbers jx of the cells of the memory 2 of its i-th column, in which the arrival of the information is recorded, and in another bit, the address number I of the corresponding column of the memory of the memory 2, which can correspond to the number of the controlled object.

5 The change of the mappings of the addresses I occurs at the end of the flashing of the numbers of all the cells j of the column I, in which the arrival of information — the signal 1 — is recorded.

After the formation of the signal O at the output of the pulse driver 15 at the output of the counter 5, the code 0 ... 0 is present, the switch 12 switches to the transmission of a co5 DRV from the counter 5 to the address inputs of the memory block 2. Signals 0 ... 0 in memory block 2 read signals O, since, as mentioned above, the io information is not recorded in the column-io. Therefore

0 a signal 1 is generated at the output of the element OR NOT 10, which permits the passage of pulses from the generator leaving 14 pulses through the element 9. After the appearance of the signal O, pulses with frequencies fB4 f lf are generated at the output of the resolution of this generator. The first pulse of the gvc and fn4 signals appears at a time equal to their period, respectively. In this case, the frequency pulse feq passes through the element And 9 and the element

OR 4 to the counting input of the counter 5, increasing its contents by one. Accordingly, the outputs of memory block 2 receive the information of its next column I. If during the recording of information from information input 1, not a single information signal (signal 1) arrived at memory block 2, then the contents of memory 2 is O. In this case, the described process of changing the addresses generated by the counter 5 is repeated until the completion of its first cycle. At the end of this cycle, the voltage drop at the output of the higher bit of counter 5 of 1 in O is fed to the trigger input of trigger B, at whose information input due to the delay of the signal from the pulse generator 15, the delay element 13 still retains signal 1. For this the condition TC n / fB4 must be fulfilled. Ta, where G3 is the signal delay time; n is the number of addresses of memory block 2. Thus, the trigger B switches to state 1 and sets the counter 5 to the state O. Consequently, in one section of the display of the information display unit 11, O will be displayed according to the counter code 5. The counter codes change .5 with the frequency fB4 not can be fixed by the operator due to the inertial properties of the human vision (at fen 1 MHz). In another resolution of the display panel of the information display unit 11, in this case O will also be displayed. This follows from the fact that the control inputs of the generator 3 of the cyclic code receive signals O, due to which the outputs of the controlled distributor 18 pulses will be absent information pulses and at the output of the encoder 19 a code 0 ... 0 is formed. A highlight of two zeros on the display of the information display unit 11 indicates

06No information about the malfunction of the controlled object.

When the signal O on the control input 16 of the device, the flashing of two zeros on the display of the information display unit 11 continues to the next (external, from the button) start of the launch unit 8. At signal 1, the control input 16 of the device automatically restarts the device as follows. Since the output of the trigger 6 is a signal 1, the first pulse of the generator 14 pulses with a frequency Tnch passes through the element And

7 to the input block 8 run.

Therefore, in the absence of information about the malfunction of the controlled object at the information input 1

The devices in the automatic mode are periodically displayed on the scoreboard of the information display unit 11 two zero during the time determined by the signal period of the T of the signal (for example, 2 s), and during the reception of the information the scoreboard is extinguished.

If during receiving information some cells of memory block 2 will be set to 1, then the addresses of columns I.

0 in which information is not recorded, in the result highlighting mode will change at the frequency fes until signal 1 appears at least at one of the outputs of memory 2. At the same time, at the output of the element OR5 NOT 10 O, which prohibits further passage of the pulses of frequency fB4 through element 9. And the device, thus, the next effective pulse will be the first pulse of the frequency T of the generator 14. At the same time, the second condition is imposed on the value of the delay time of the delay element 13. With the worst distribution of information in this case (units in,

5 cells of memory block 2) only in any one cell of the column whose address corresponds to the counter code 5, equal to 1 ... 1, trigger 6 when the first impulse of the generator 14 to the counter 5 is received through the global controller 3, the cyclic code and the element OR 4 does not switch, because at this time its O signal will be present at its information input.

In this case, the passage of the first pulse fH4 of the generator 14 (worst) through the cyclic code generator 3 is due to the cyclical nature of its controlled pulse distributor, whose operation cycle is determined by the expression - m / fW, where m is the number of control inputs to which the signal goes 1. In this case, the device will not restart through the AND 7 element at any signal at the control input. sixteen

5 devices, and the addresses of block 2 of memory will change with the frequency of the ghw when the contents of the corresponding column are equal to O in all J-th cells, or with the frequency of the nn with the contents of at least one cell J,

0 equals 1 of the corresponding column. At the same time, the change of the numbers that determine the address of the columns of the memory block 2, where

1 that scoreboard of display unit 11 is determined by the duration of the cycle

5 TCs shaper 3 cyclic code. Those. during the flashing of the address of the column containing m cells with recorded information (1), there is a sequential change of m numbers, displaying the numbers of the j-th

cells of this column. Each pulse of the end of the code generation cycle changes the address of memory block 2 by incrementing the contents of counter 5 by one.

Highlighting the numbers of columns and cells containing the recorded G, indicating the malfunction of the monitored object, will continue until the next external launch of the launch block 8.

The device allows controlling a large number of objects of the same type with their numbering on one bit of the scoreboard of the information display unit 11 and localization of the malfunction (for example, the parameter number) on another bit of the scoreboard, which increases the information content of the device.

Formula from the acquisition Device for signaling state-objects, containing a memory block, the outputs of which are connected to the inputs of the OR-NOT element, a pulse generator, the first output of which is connected to the first input of the first element AND, the second input of which is the input control unit, and the output is connected to the input of the start-up unit, the output of which is connected to the recording input of the memory flare zeros, the counter, the outputs of which are connected to the address inputs of the information displaying unit, and the switch, so that, with a view to elevated and informativeness of the device, the pulse shaper, cyclic code shaper, trigger, second AND element, OR element and delay element, output

the trigger unit is connected to the input of the pulse generator, the output of which is connected to the gating input of the information display unit, to the installation input to the 0th trigger, to the control input of the switch and to the input of the delay element whose output is connected to the information input of the trigger, whose output is connected to the third input of the first element I and with the installation input into O of the counter, the output group of which is connected to the first group of information inputs of the switch, the outputs of which are connected to the address inputs of the memory unit, information These inputs are the information input of the device, the second group of information inputs of the switch is the address input of the device, the output of the OR element is NOT connected to the first input of the second AND element, the second input of which is connected to the second output of the pulse generator, and its output to the first input of the element OR, the output of which is connected to the counting input of the counter, the output of the higher bit of which is connected to the trigger synchronization input, the output of the end of the loop of the cyclic code generator with the second input of the element A and outputs the block memory - with information vhrdami conditioners cyclic code group whose output is connected to a group of information inputs information display unit, the first pulse generator output coupled to an input of the synchronization code shaper cyclic.

Claims (1)

Claim A device for signaling state-objects, containing a memory block, the outputs of which are connected to the inputs of the element OR-HE, a pulse generator, the first output of which is connected to the first input of the first element And, the second input of which is the control input of the device, and the output is connected to the input of the block launch, the output of which is connected to the input of the recording of zeros of the memory block, the counter, the outputs of which are connected to the address inputs of the information display unit, and a switch, characterized in that, in order to increase the information content of the device, a pulse shaper, a cyclic code shaper, a trigger, a second AND element, an OR element, and a delay element, the output of the trigger unit is connected to the input of the pulse shaper, the output of which is connected to the gating input of the information display unit, with the input to the trigger setting 0, with a control input switch and with the input of the delay element, the output of which is connected to the information input of the trigger, the output of which is connected j to the third input of the first element And and with the installation input to 0 of the counter, the group of outputs of which connected to the first group of information inputs of the switch, the outputs of which are connected to the address inputs of the memory block, the information inputs of which are the information input of the device, the second group of information inputs of the switch is the address input of the device, the output of the OR-HE element is connected to the first input of the second element And, the second input which is connected to the second output of the pulse generator, and its output is to the first input of the OR element, the output of which is connected to the counting input of the counter, the output of the highest order which connected to the trigger synchronization input, the output of the end of the cycle of the shaper of the cyclic code - with the second input of the OR element, the outputs of the memory block - with the information inputs of the shaper of the cyclic code, the group of outputs of which is connected to the group of information inputs of the information display unit, the first output of the pulse generator is connected 35 with the synchronization input of the cyclic code generator.