SU1635266A1 - Device for monitoring discrete channels - Google Patents

Abstract

The invention is from a poet to an “-surface connection. Bel of the invention is the control accuracy by comparing the durations of the control and transmission cycles. The device contains a block 1 for calculating read and write memory, block, write block, memory 3 and memory 4, trigger 5, blocks 6 and 7 comparisons, counter 8 and 9, generator 10, counter 11 clock pulses, and tribe H 12. As soon as the counter 8, which calculates the output pulses and the formform during the transfer time, is set to the position equal to the number of the antigenic device i in block 4, then a logical O will be set on the output of the button 7, in which block 2 is set to the Norm state . 1 il.

Description

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The invention relates to telecommunications and can be used in data transmission systems for monitoring channels and transmission paths.

The purpose of the invention is to improve the control accuracy by combining the durations of the control and transmission cycles.

The drawing shows the structure on the electrical circuit of the device for monitoring data channels

The device contains a block 1 calculating the address difference of the record and read

nor, block 2 alarm, blocks 3

and A memory, trigger 5, blocks 6 and 7 of comparison, counters 8 and 9, generator 10, estimator 11 clock pulses and element 12.

The device works as follows.

Initially, the installation parameters of the control device in block 4 are set. The installation of the code corresponding to the continuously selected control cycle Ste is set. This code is fed to a multiplexer included in the 11-clock counter to select the appropriate divider output. At the same time, the duration of the data channel monitoring cycle is chosen equal to the duration of the specified information transfer rate. Counter tn The code number is also set equal to the number of information blocks that must be given to the recipient during the time equal to the transfer rate duration to ensure the data link operability.

From the output of block 1, signals about issuing information blocks to the recipient are received at the input of counter 9. Block 1 calculates the difference between the write and read addresses of the managed memory (not shown), the write address is numerically equal to the cyclic number of the received block, and the read address is according to the block number issued to the recipient. Thus, the difference between the number of information blocks received from the channel and issued to the recipient is determined. A signal from the output of block 1 is fed to the input of block 3 of memory.

At the beginning of each cycle, from the output of the generator 10, the pulses go to the input of the counter 11. From the output of the counter

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11 pulse records the state in block 2 of Avari. In addition, the pulse resets the counters 8.9 and trigger 5, as well as recording in memory block 3 a number equal to the difference in the number of information blocks received from the communication channel and issued to the receiver.

As soon as the counter 9, which performs the counting of information output pulses, is set to a position equal to the number stored in memory block 3, the comparison block 6 will work, followed by trigger 5. This indicates that the information blocks delayed to the beginning of the current control cycle (transmission rate), issued to the recipient. After triggering the trigger 5, the output pulses of information from the output of block 1 through the element 12 will be fed to the input of the counter 8.

As soon as the counter 8, which counts the output pulses of information at the current rate of transmission, is set to the position set in block 4, the output of block 7 is set to a logical O, according to which the signaling unit 2 is set to Norm. If the number fixed by the counter 8 is less than the number set in block 4, then the alarm block 2 will save the state of Avari set at the beginning of the current monitoring cycle. When the next pulse arrives from the counter output of 11 clock pulses, the alarm state will be fixed in alarm block 2 and displayed on the display.

Claims (1)

Invention Formula A device for monitoring discrete channels, comprising a first counter, a signaling unit, a serially connected generator and a clock counter, serially connected trigger and an element, characterized in that, in order to improve the accuracy of the counter by combining the durations of the monitoring and transmitting cycles, the first memory block is entered These, in series, the block for calculating the difference between the write and read addresses, whose input is the input of the device, the second counter and the first comparison block, you are 5 1635266 the course of which is connected to the first inputs of the first comparison unit, to the trigger input, successively the coi-second inputs of the clock counter and the second memory block and the auto-pulses are connected to the second corresponding comparison block, the second inputs are connected by the second outputs they are connected to the corresponding 5 memories, and the output is connected to another the outputs of the first counter, the first input of the second counter, to another the input of which is connected to the output of the first memory block, to the second element I, the other input of which from the trigger input to the second input one with the first output of the first 1 compute-1Q block and to the first input the laziness of the difference of addresses of the record and the alarm signaling block The first memory block is connected to the other unit of comparison.