SU1665399A1 - Multichannel device for information transmission and compression - Google Patents

Abstract

The invention relates to computing and can be used in multi-channel systems for transmitting and receiving information. The purpose of the invention is to increase the compression ratio of the information and the speed of the device. The device contains a clock, a counter, a multiplexer, an analog-to-digital converter, the first and second memory blocks, the first and second blocks of the address generation, the first and second blocks of determining the priority of signals, the elements And, the first and second computing blocks, the bus driver, the first and a second block for transmitting and receiving information, an information output block. 3 il.

Description

The invention relates to computing and can be used in multi-channel systems for transmitting and receiving information. 0

The purpose of the invention is to increase the compression ratio of the information and the speed of the device.

The drawing shows the functional diagram of the device.

The device contains a clock pulse generator 1, a counter 2, a multiplexer 3, an analog-to-digital converter (ADC) 4, the first memory block 5, the first 6 and second 7 blocks of forming the address, the second memory block 8, the first 9 and second 10 blocks of determination signal priority, the first 11 and second 12 computing units, the bus driver 13, the first 14 and second 15 blocks of transmitting and receiving information, elements 16-21 and block 22 of the information output, information inputs 23, initial setup 24 and output 25 of the device.

The device works as follows.

The reset signal at input 24 of the device is reset to counter 2 and blocks 11 and 12. Then, pulses from generator 1 trigger ADC 4 and recalculate with counter 2 to digitize the time, while the lower bits of counter 2 are used to switch the input analog channels through multiplexer 3.

The multiplexer 3 polls the input channels, and information from the information inputs 23 of the device is sequentially fed to the input of the ADC 4.

From the output of the A / D converter 4, a digital code corresponding to the value of the analog signal parameter is recorded in the successive cells of the first memory block 5 in accordance with the structure,

O5

about ate

00

with so

presented in table.1. The eight-bit binary code of the analog signal for each channel is recorded in 16-bit memory slots of two channels in each cell. The accumulation of cell addresses for recording a digital code is performed using a counter. This output of counter 2 is connected to the address inputs of the first memory block 5 through the address generation block 6. Block 6 connects the address either from the counter 2 or from block 11 to the memory block S using an enable signal. The frequency generated by the block 9. Frequency the write access to memory block 5 is determined by the frequency of generator 1. At the same time, the connection time of analog channels in LIC 4 and for recording in memory block 5, corresponding to a generator 1 period, exceeds the possible service waiting time at block 9. As a result of loss of information etc there is no treatment processes. Simultaneously with the recording of information in block 5, the information from this block is read by the calculating block 11 for processing. In order to read from block 5, you need to know the time code and write address of the analog parameter. For this, the state of the counter 2 is read through the bus driver 13 by referring to the latter by the INADR command of the block 11.

The separation in time of recording and reading information from memory block 5 is performed by block 9. The processing of information recorded in memory block 5 is performed by computing block 11 "

If a significant measurement is detected on one of the channels, its new measurement is recorded in the previous one, and this significant measurement, together with the address and time code, is recorded in memory block 8 by reference from the first computing unit 11 according to the structure presented in Table 2. In this case, the time code corresponds to the current time value, the read address contains information about the channel's nermer and the time of writing this information to memory block 5. Since the period of the generator is known - Tr,

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can be identified by the code (C) of the counter 2 entries and the address of the reading ABR. parameter recording delay time with respect to the recorded time code D (C / m-ADR,}) Tr. Then the recording time of the input analog signal is determined as follows:

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-D.

0

five

0

five

five

All the above calculations to determine the actual recording time of a parameter are made by a computing unit 12, which forms an information output frame consisting of the recording time of the information and the parameter itself. This information output frame is converted into a serial code using the information output unit 22. The time separation of the access times to the second memory block 8 from the first 11 and second 12 computing blocks is performed using block 10. The appeal to the second 8 memory block is decrypted using elements 18 and 20, the signals from which are sent to the second block 10 The signals at the inputs of the block 10 control the operation of the address generation block 7, which switches to the address inputs of the memory block 8 or the first or second computing blocks, dividing them in time.

To process and write information to the memory block 8, the first computing block 11 needs to know the readout address, which is

0 in the general registers of the second computing unit 12, and for the latter to work, it is necessary to know the address of the entry that is in the general registers of the first

5 of a computational unit 11. / 1l of exchanging such information, blocks 14 and 15 are intended, the access to which is decrypted on elements AND 19 and 20. Forwarding the address of the record to the second computational unit is organized as follows. Appeal to block 15 block 12 programs it

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in mode 1 for register Viv mode 2 for register A, then writes information into register B, which is transmitted to block 11 as an interrupt vector. Having processed this interrupt, block 11 reads the address of the record from its general register and sends it to register A of block I. Since register k is programmed in mode 2 for both blocks and 15, the information recorded in one register is transferred to another, therefore becomes available for block 12. Block 12, after requesting an interrupt through register B of block 15, enters the scanning mode of the sign of recording information in register A, this sign is located in register C of this block. As soon as a sign of recording information in register A appears, the contents of this register are read into block 12, so this block recognizes the address of recording information in block 8 of memory. Using the same algorithm, block 11 recognizes the address for reading information from memory block 8, only the direction of the request and transmission of information is reversed.

In the process of compressing information, block 11 constantly monitors the degree of filling of the second memory block 8. As soon as the degree of filling of the second memory block exceeds 80%, block 11 switches to a more complex compression algorithm, for example, from an algorithm comparing absolute values of signal parameters to an algorithm using the first derivative. The fact of transition to a more complex algorithm, for example, using the first derivative, is recorded by the unit in the channel measurement cell at the place of the lower bit of the high byte (Table 2). The transition to an even more complex algorithm causes the unit to move in the high byte of this cell by another bit up, and so on.

Thus, the use of computing blocks for processing information allows the use of an algorithm of any complexity and increase the speed of the entire device.

Claims (1)

Invention Formula A multi-channel data transmission device with compression, containing a multiplexer, the information inputs of which are information inputs of the device, the output of the multiplexer is connected to the information input of the analog-digital converter, the outputs of which are connected to the information inputs of the first memory block, the outputs of which are connected to the information inputs / outputs of the first computational unit, the clock generator, the output of which is connected to the clock input of the analog-digital converter, the counter, the corresponding outputs of which are connected to the address inputs of the multiplexer, the information output unit whose output is the output of the fact that, in order to increase the compression ratio of information and speed, it 5, the second memory block, the second computing unit, the bus driver, the first and second signal priority determining units, the first and second address generation units, the And elements, the first and second information transmitting and receiving units, the output of the clock generator connected to the clock inputs of the first the priority signaling unit and the counter, the last reset input and the reset inputs of the first and second computing units are combined and are the input of the initial installation of the device, the corresponding counter outputs By connecting the inputs of the first group of address inputs of the first address generating unit and to the inputs of group of information inputs of the bus shaper, 5 outputs of which, information inputs of the second memory block, inputs of a group of inputs and inputs-outputs of the first group of inputs and outputs of the first transmission and reception unit of information are combined and connected to information inputs and outputs of the first computational unit, outputs of the first group of outputs of the latter are connected to inputs groups of inputs of the first, 5 of the second, third and fourth elements I, the inputs of the second group of address inputs of the first address generation unit and the inputs of the first group of address inputs of the second address generation unit, the corresponding output and outputs of the second group of outputs of the first computing unit are connected to the inputs of the first, second, third, fourth elements And to the inputs of the first group of control inputs of the second block forming the address, respectively, the outputs of the first, second, third and fourth elements And are connected to the control input of the first signal priority block, the bus driver resolution input, the first control input of the second signal priority block and the resolution input of the first transmission and reception unit, respectively, the first and second outputs of the first signal priority block, are connected to the first and the second control inputs of the first address generation unit, respectively, the outputs of the group, the first and second outputs of which are connected to the address inputs, to the read and write inputs of the first memory block with Respectively, the outputs of the second memory block, information inputs of the information output block, group inputs and inputs-outputs of the first group of the second information transmission and reception unit are combined and connected to the inputs-outputs of the second computational unit, the outputs of the first group of the second computational unit are connected to the inputs the second group of address inputs of the second address generation unit, to the address inputs of the information output unit and to the inputs of the groups of the fifth and sixth elements AND, the corresponding output and outputs of the second group of the second computational unit is connected to the inputs of the fifth, sixth elements And, to allow the input of the information output unit and the inputs of the second group of control inputs of the second address generation unit respectively, the outputs of the fifth and sixth elements And are connected to the second control input of the second signal priority determining unit and to the enable input of the second transmission and reception unit respectively, the first and the second outputs of the second signal priority determining unit are connected to the first and second control inputs of the second address generation unit, respectively, the group outputs, the first and second outputs which are connected to the address inputs, to the read and write inputs of the second memory block, respectively, the outputs of the first and second signal priority determination blocks are combined and connected to the Ready input of the first computing unit; the fourth output of the second signal priority determination unit, connected to the Readiness input of the second computing unit, the fumes of the groups and the outputs of the first and second Transmit and Receive Information blocks are connected to the information inputs and to the interrupt inputs of the second and first computing blocks respectively, the inputs and outputs of the second groups of the first and second blocks of transmission and reception of information are combined. i Table 1 2 4 6 8 10 12 T 16 18 20 22 2 "1 32 2 7 ten eleven 12 15 sixteen Time desecond yod „m. sex AND channel measurement table 2 unit minutes Des.minutes unit hours des.sec sot.msek unit seconds record counter reading address read write address o (i) o 000000