SU1647881A2 - Digital pulse-width modulator - Google Patents

Abstract

The invention relates to automation and computing, can be used in measuring and conversion systems of communication and control and is an improvement of the device. described in ed.St. №1478316. The purpose of the invention is to increase the reliability of the device. The device contains two pulse counters, three counting triggers, a square pulse generator, four coincidence elements, two pulse generators, an inverter, three OR elements, two switches, a limiting unit, a reset unit, a symbol bus, an input signal bus, four NAND elements , eight galvanic isolation elements, four power switches, four current sensors, a power bus, a load bus and a zero potential bus. The goal is achieved by preventing the occurrence of short circuits in the power section by controlling the current flowing through the power switches. 2 Il.

Description

The invention relates to automation and computing, can be used in measuring and conversion systems of communication and control and is an improvement of the invention according to the author. N: 1478316.

The purpose of the invention is to increase the reliability of the device.

FIG. Figures 1 and 2 present a structural electrical modulator circuit.

Digital pulse-width modulator contains counters 1 and 2 pulses, counting triggers 3-5, trigger 6 characters, generator 7 rectangular pulses, elements 8-11 coincidence, drivers 12 and 13 pulses, inverter 14, elements OR 15-17, switches 18 and 19, restriction unit 20, reset unit 21, bus 22 characters, input signal bus 23, AND-NOT elements 24-27,

galvanic isolation elements 28-35, power switches 36-39, current sensors 40-43, power bus 44, load bus 45, and zero potential bus 46.

The modulator operates as follows.

After switching on the supply voltage, the reset unit 21 generates a signal that sets the counting triggers 4 and 5 to zero, gates through the matching element 11 the counters 1 and 2 and then gates through the inverter 14 the flip-flop 6 characters. In this case, the input signal, having passed through the limiting unit 20, is recorded in a forward (with a positive signal) or in a reverse (with a negative signal) code in counter 1, and the sign code of this signal is recorded in flip-flop 6 characters.

About Ј XI

oo with

KZ

Depending on the sign of the input signal on bus 22, the generator pulses of 7 rectangular pulses with a frequency f0 pass either through the element OR 15 (the sign is positive) or through the element 16 OR (the sign is negative) and are received respectively either at the direct count input or to the countdown counter 1 input. Depending on the size of the input signal mantissa on the transfer outputs (either on the forward or reverse) of counter 1 after a period of time

(2n-n)

where n is the number of bits of the binary counter;

N is the mantissa of the input number, after the initial setting (gating) a negative pulse appears.

This negative pulse from the output of the counter 1, having passed through elements 8, 17 and 9, is fed to the input of the counting trigger 4 and switches it. The same impulse, passed through elements 12 and 10, is fed to the input of the counting trigger 5 and switches it with a time delay τ relative to the trigger switching 4. The delay time τ is determined by the driver of 12 pulses. Square pulses from the generator 17 square pulses are also fed to the input of the counting trigger 3, which divides the frequency f0 by 2. Right. fo

coal impulses with a frequency from the counting trigger 3 are fed to the counting input of the counter 2. At the transfer output of the counter 2

2n +1

after a period of time - gpo

Thats

barely the initial setup, a negative impulse appears which, having passed through the coincidence element 10, is fed to the input of the counting trigger 5 and returns it to its original state. the driver 13 arrives at the input of the counting trigger 4 and also returns it to the initial state. A negative pulse from the output of counter 2 through coincidence element 11 is valid for counters 1 and 2 and through inverter 14 for trigger 6 of the sign. The process repeats. Thus, the device enters the automatic gating mode. In this case, from the outputs of switches 18, 19, direct and inverse sequences of pulses with a period arrive:

T t2 -

n +1 a

Moreover, taking into account that trigger 4 receives an inverse signal from the first inputs of switches 18.19, and a direct signal from trigger 5 to their second inputs, then between the fronts of the direct and inverse pulse sequences are spacing of duration t and ha . It's obvious that

(2n-n)

five

0

0

five

must be greater than ti, otherwise a pulse width modulation will fail. For

g providing this condition, a limitation unit 20 is inserted in the device, which prevents the input signal on the tires 23 from exceeding the predetermined value NAon.

QSignals from the outputs of the switches 18 and

19 through the elements of the NE-24 and 25 through the galvanically isolated elements 32-35 are fed to the control inputs of the power switches 36-39 (for example, transistor), in a closed circuit of which 40-43 current sensors are connected, connected through the elements 28-31 of the galvanic isolations with AND-NOT elements 26 and 27, which compare the currents in the diagonal x of the power bridge. In emergency

In a situation where currents begin to flow simultaneously in both diagonals of the bridge, a logical zero signal is generated at the output of the AND-NE elements 26 and 27, which is fed to the inputs of the AND-NE 24 and 25 elements.

This signal is prohibited for the control signal and a high level signal is constantly present at the output of the AND-NE elements 24 and 25 as long as currents flow simultaneously in both diagonals of the bridge. Thus, prevention of the occurrence of short circuit modes is ensured by controlling the current flowing through the power switches, which increases the reliability of the device operation.

Claims (1)

Invention Formula Digital Pulse Width Modulator auth.St. Mg 1478316, characterized in that, in order to increase the reliability of the modulator, the first, second, third, and fourth elements of AND-NOT, the first, second, third, fourth, fifth, sixth, seventh, and eighth elements are introduced into it galvanic isolation elements, the first, second, third and fourth power switches and the first, second, third and fourth current sensors, the inputs of which are connected to the outputs of the corresponding power switches, and the first outputs through the corresponding elements of electrical isolation connected respectively to the first and second inputs of the third NAND element and to the first and second inputs of the fourth NAND element, the output of which is connected to the first inputs of the first and second NAND elements. the second inputs are combined and connected to the output of the third NAND element, and the third inputs are respectively connected to the outputs of the first and second switches, while the information inputs of the first and fourth power switches are combined and are the power bus, the information inputs of the second and third power switches are connected respectively to the second outputs of the first and four FF -iJ0 five current sensors are the load buses, the second outputs of the second and third current sensors are combined and are a zero potential bus, the inputs of the fifth and sixth elements of the galvanic isolation are combined and connected to the output of the first AND-NOT element, and the outputs are respectively connected to the control inputs of the first and third power switches, the inputs of the seventh and eighth elements of galvanic isolation are combined and connected to the output of the second element AND-NOT, and the outputs are respectively connected to the control inputs of the fourth and a second power switches. Fig 1