SU1187275A1 - Digital-to-pulse width signal converter - Google Patents

Description

The invention relates to the field of pulse technology and can be used in automation devices for communicating digital calculators (microprocessors) with executive mechanisms.

The purpose of the invention is to increase the noise immunity and the expansion of the limits of regulation.

The drawing shows the structural, 0turnuyu electrical circuit converter.

The converter contains a pulse generator 1, a binary counter 2, a digital comparator 3, a buffer, 5 register 4, a decoder 5, an IS-NE 6 element, a trigger 7, an integrating element on condenser 8, an inverter 9, bus. 10 input code and output bus 11. 20

The output of the pulse generator 1 is connected to the counting input of the binary counter 2, whose discharge outputs are connected to the corresponding ones. the first inputs (D] of the digital comparator 3, to the second inputs (B) of which the corresponding outputs of the buffer register 4 are connected, the inputs of which are connected to the buses 10 of the input code, the output of the digital comparator 3 through the first input of the AND-HE element 6 is connected to 5 -input ZK-trigger 7, the second input element AND-NOT 6'connected to the output of the decoder 5, the inputs of which are connected to the corresponding outputs of the digits of the binary counter 2, between the b - and 3 -inputs ZK trigger 7 connected integrating element on the capacitor 8, and the output of the binary transfer etchika 2 through the inverter 9 is connected to the K inputs -and 5-flop 7, whose output is connected to output line 11.

The Converter operates as follows.

Binary counter 2 cycles through all its 2 ^P states, where H is the number of digits of the counter. When binary counter 2 reaches the state А -b, where B is the converted code from buffer register 4, a pulse is generated at the output of digital comparator 3, which passes through the AND-HE6 element with its leading edge, resets the ZK trigger 7 to zero. In this case, a unit from the output of the decoder 5 is supplied to the second input of the element AND-NOT 6.

When binary counter 2 overflows, an overflow signal appears at its transfer output, which, with the falling edge, sets ACK-TRIGGER 7 to one state. Further processes are repeated.

The presence of the signal "0" from the decoder 5 at the input of the element AND-NOT 6, if there are ones in all digits, prohibits resetting the LC of the trigger 7 to zero at the maximum convertible code B = 11 ... 1 and ensures stable operation of the converter with a duty cycle of 1, extending the limits of SIS regulation. The presence of the integrating capacitor 8 between 5 and 3 inputs of the trigger 7 provides the necessary protection of the converter from impulse noise of short duration.

For example, when the code on register 4 equals 8 = 1 1 ... 1, a positive polarity signal is generated at the output of digital comparator 3, and a negative polarity signal is disabled at the output of decoder 5. When this occurs, the state of the edges of the signals and at the output of the element AND-NOT 6 may appear a signal of short duration on the leading or trailing edge of these signals.

In the absence of the integrating capacitor 8, a false triggering of the 5 K-trigger 7 occurs.

Thus, the proposed device provides a high noise immunity and a wide range of regulation of the duty cycle of output pulses from 0 to 1 with a resolution equal to the pulse period (Τη) from the pulse generator 1, and the repetition rate of the output pulse-width signal

one

1187275

Claims (2)

CODE CONVERTER - WIDE-PULSE SIGNAL, containing OK-trigger, inverter, pulse generator, the output of which is connected to the counting input of the binary counter, the output of which is connected to the first inputs of the digital comparator, the second inputs of which are respectively connected to the outputs of the buffer register, the inputs of which are the input code buses, the decoder, the inputs of which are connected to the corresponding outputs of the bits of the binary counter, characterized in that, in order to increase the noise immunity and broadening the limits of the regulation of the duty cycle of output signals, an element of the NAND and an integrating element made on a capacitor, the first lining of which is connected to the output of the NAND element and 5 to the в input of the trigger, and the second lining to the common bus and I to input 3 to the trigger, the output of which is the output bus, and the k and C inputs are combined and connected to the output of the inverter, the input of which is connected to the transfer output of the binary counter, the first input of the Y-NOT element connected to the output of the digital comparator, and second entrance - to exit de the encoder. Ka 1187275 > 1 1187275 2